Test Clock Frequency Research Articles

Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects

Optimal Test Clock Frequency Based Test Option Generation for Small Delay Defects

Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation

Three-dimensional Integrated Circuits (3D IC) are being looked at as an alternative in overcoming some critical challenges plaguing conventional 2D ICs. However, it faces some new challenges — some of them being thermal management and a complicated testing process. This work presents a frequency-scaled thermal-aware test scheduling algorithm for 3D ICs. The thermal awareness is provided by a proposed machine learning based predictive thermal estimation model for 3D ICs. The proposed test scheduling algorithm includes test clock frequency as an important parameter and scales the frequency to achieve lower test time. Experimental results for both the predictive thermal model and scheduling algorithm look promising, with improvements over existing works achieved in most of the cases. The thermal model estimates the temperature of a 3D IC with a high degree of accuracy but at a fraction of time of commonly used 3D IC thermal models, while the scheduling algorithm has been observed to have improved test time of different benchmark circuits up to around 60%. Experimental results show — that test time in terms of clock cycles is inconsequential because schedules with higher clock count may require less time due to frequency scaling.

NBTI and HCI Aging Prediction and Reliability Screening During Production Test

With the semiconductor manufacturing technology approaching to 14 nm and below, the reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging mechanisms, including negative bias temperature instability (NBTI) and hot carrier injection (HCI). Furthermore, significant process variations differ the aging degradation rate of each individual IC, which causes significant failure time differences even for the ICs belonging to the same lot. Therefore, to select devices for the applications with various reliability requirements, it is necessary to conduct efficient predictive reliability screening during production test at time-zero. In this article, a fast time-zero aging prediction and predictive screening methodology based on a novel on-chip architecture named ZeroScreen is proposed. The pattern-based aging screening time is limited to 8.14 ms per device considering 50-MHz test clock frequency and 6.6- $\mu \text{s}$ automatic test equipment (ATE) voltage settling time. In the experiment, fresh 45-nm FPGA devices and 130-nm ASIC chips are projected into four reliability bins with ZeroScreen-based aging prediction at time-zero. According to the silicon data, the reliability screening errors of ZeroScreen for the 45-nm FPGA chips are less than 6.5% and 4.3% for static and dynamic stress cases, respectively. And the screening errors for the 130 nm ASIC chips are close to 0, for both static and dynamic stress cases.

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

With shrinking device sizes, System-on-Chip (SoC) cores are growing in number and complexity. This has led to high volumes of test data and long test times. Therefore, reducing test cost by minimizing the overall test time is one of the main goals of SoC testing. To efficiently manage test resources and power dissipation, tests for the SoC cores are arranged into test schedules. Traditional SoC test methods assume a constant test frequency and supply voltage (VDD) for the entire test schedule. However, test power and test time can be regulated by varying VDD and test clock frequency to optimize SoC test schedules for a given power budget. The research presented in this paper focuses on power-aware optimization of SoC test schedules to minimize test time by scaling the supply voltage and test clock rate. This scaling can be on a per session basis (in case of session-based test schedules) or dynamically (in case of sessionless test schedules). Exact and heuristic algorithms for solving the optimization problem are discussed. These algorithms are implemented and applied to several SoC benchmarks. Results show a significant reduction in SoC test time over the conventional test schedules where VDD and clock are fixed at given nominal values.

Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells

The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing

The total logic activity produced in a digital circuit during testing, and hence the total energy consumed, is an invariant of a set of tests. Faster we consume this energy, shorter will the test time be. Thus, to minimize the test time we may maximize the power during test by using a dynamically selectable clock frequency. This idea is exploited in our solution for the problem of finding clock frequencies under the constraints of maximum allowable power and critical path delay. A very efficient but approximate kth-root solution finds k test clock frequencies, which are further optimized by a locally exhaustive search (LES) algorithm. Both solutions have an O(N×k) complexity for finding k clock frequencies when the test runs through N clock cycles, though kth-root solution is about two orders of magnitude faster to compute than LES. In practice, LES gives optimally minimum test time and is matched by the kth-root solution for k ? 10.

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-onchip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

This paper presents a design for testability (DFT) technique for testing high-speed circuits with a low-speed test mode clock. With this technique, the test mode clock frequency can be reduced with virtually no lower limit. Even with the reduced speed requirement on the automatic test equipment (ATE), our method facilitates the test of the rated-speed timing and allows performance binning. A CMOS implementation of the DFT hardware with 50 ps timing accuracy is presented. To demonstrate the effectiveness of the technique we designed a 16-bit, 1.4 GHz pipelined multiplier as a test vehicle. Simulations using a test clock frequency much lower than the rated clock frequency show that delay faults of sizes as small as 50 ps are detected and that the new test technique provides correct performance binning.