Test Circuit Research Articles

Studi Kelayakan Gas Insulated Switchgear di PT. Paiton Operation & Maintenance Indonesia Unit 8

Protection systems are a collection of components that have the same purpose to protect or secure. One of the existing protection systems in the generator is switchgear. At PT. Paiton Operation & Maintenance Indonesia Unit 8 using a switchgear insulated with SF6 gas is called gas insulated switchgear. Gas Insulated Switchgear is the newest of the Switchyard innovations. Innovations that have been developed from air isolation into gas insulation have fewer land use advantages and a better level of density. In determining the feasibility of gas insulated switchgear PT. Paiton Operation & Maintenance Indonesia performs tests consisting of insulation resistance measurements, resistance measurements, gas leakage checks, polarity checking, gas density detectors, testing duration closure and circuit breaker opening. Each test has a pre-defined value limit. Gas Insulated switchgear is said to be feasible to operate when it meets the specified value limits on each test.

A Design and Validation of 400 W PV Emulator Using Simple Equivalent Circuit for PV Power System Test

In this paper, we propose a photovoltaic emulator (PVE) composed of a series of connected power diodes with a single constant current source, rather than a power converter-based PVE. Accordingly, this enables readily verifying the operation because a the simple hardware structure and lack of a complex control algorithm. The proposed PVE can be intuitively implemented using the proposed selection criteria for the power diode and equivalent resistances. Since there is no feedback control based on complex analog/digital controls and sensors, the control response can be very fast. In addition, the proposed PVE can be easily integrated with a PV power system such as a power optimizer, to allow testing in a simple and flexible manner. Spice simulation was performed based on the electrical characteristics provided by the solar panel manufacturer, and this was utilized to validate the applied emulator circuit model, the Norton Equivalent Circuit. During the design process, the simulation helped to manufacture the PVE within error ranges satisfying the desired I–V and P–V curves, as well as the maximum power point (MPP). Partial shading could be easily implemented through use of the multiple series connection of individual PVEs, demonstrating local MPP and global MPP. A 400 W class PVE was built through appropriate power diode selection, with a thermal design to increase the output power. Moreover, its performance and feasibility were verified through intensive experiments. The measured efficiency, transient response time, and maximum transient error of the partial shading tests were 91%, 22 μs, and 5.8%, respectively.

Research on the Switching Characteristics Based on the SiC MOSFET Model

With the continuous development of power electronics technology, the third-generation semiconductor materials represented by SiC and GaN have significant advantages in the band gap width, breakdown electric field, thermal conductivity, electron saturation rate and other key parameters, which meet the needs of modern industry for high power, high voltage and high frequency. When the SiC MOSFET plays its high frequency advantage, with the increase of switching frequency, the voltage change rate and current change rate of the device will be larger in the process of turning on and off. This paper mainly analyzes the characteristics of SiC MOSFET devices, and modifies the model based on the model provided by the manufacturer. By establishing static and dynamic test circuits, the static characteristic curves of the model were observed, and the drain voltage and current waveforms of the original model and the optimized model were compared during the switching process. The results show that the switching time of the optimized model is improved, and the oscillation waveform is greatly improved. Then, the accuracy of the optimized model is verified by the double-pulse circuit, and the drain source voltage and the drain source current are studied and observed under different temperature and drive resistance conditions. This paper provides data support for improving the switching characteristics of SiC MOSFET in practical applications.

Research on the Effect of an Air-Blown Interrupting Gap to Reduce the Rate of Lightning Tripping

The air-blown interrupting gap protection method is a self-energy interrupting method based on the concept of suppressing arc building by frequency continuation. In order to verify the effect of an air-blown interrupting gap to reduce the rate of line lightning tripping, in this paper, the protection principle of the air-blown interrupter gap is first described, and the action process simulated by COMSOL Multiphysics simulation software. Next, a frequency renewal test circuit is built for the test. Then, an arc-building rate calculation model and a lightning trip rate calculation model under the condition of an air-blown interrupting gap are established, and, finally, a 10 kV overhead line in Yunnan is selected for the verification of the calculation example. The results show the following: a gas blowing arc gap can be effectively extinguished in about 2.5 ms frequency arc and with no re-ignition phenomenon. Before and after the installation of the gas blowing arc gap line, the arc rate changed from 37.27% to 4.1%, respectively, and the lightning trip rate changed from 8.64 times/(40 thunderstorm days—100 km) to 0.337 times/(40 thunderstorm days—100 km), respectively. The decline rate was more than 95%, and in actual operation, it reduced the lightning trip rate enough to achieve good results.

Analysis of Fluid Flow in a Radial Centrifugal Pump

The paper presents a validation of the results of a numerical model of radial centrifugal pump flow using a PIV (Particle Image Velocimetry) experimental method. For this purpose, a 3D model of the pump was created in Inventor, which was then used to design a numerical flow model in Ansys in the CFX module. The performance characteristics of the same pump were measured on an experimental test circuit, and vector maps of the flow in the suction pipe were obtained using the PIV method. The results of the experiment—vector fields of fluid velocity distribution in a suction pipe—were then compared with the outputs of the numerical Ansys model, namely the streamlines and pressure distributions. This comparison demonstrated that the numerical model is most consistent with reality if the input variables are the pressure in front of the pump and the mass flow behind the pump. In this case, the model can determine the pressure at the pump inlet with a deviation of 1% to 10% and create streamlines in the suction pipe corresponding to the results of PIV measurements.

Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test

This article presents design and test of three-port distributed circuit exhibiting double bandpass (BP) negative group delay (NGD) effect.

Analysis and Simulation Study on a Fault of Service Duty Test of Vacuum On-load Tap Changer

Aiming at a fault on service duty test of vacuum on-load tap changer (OLTC), the principle of the resonance test method is analyzed. Combined with the voltage and current waveform measured and the standard switching sequence, the cause and process of the test fault are qualitatively deduced. Based on the theoretical analysis, the simulation model of the test circuit and fault is built based on PSCAD. The voltage and current waveforms obtained by simulation are highly consistent with the test waveforms. The error of peak current between the simulation and the test waveform is 0.75%. The simulation results show the accuracy of the theoretical analysis and modeling calculation, they are verified by the follow-up inspection results of OLTC and vacuum tube solution. This paper provides a powerful technical means for fault analysis and fault mechanism research in the follow-up OLTC operation. It also has reference and guiding significance for the quality control, design, operation and maintenance, and monitoring of vacuum OLTC.

Development of DC Parameter Calibration Module for Digital Integrated Circuit Test System

Aiming at the on-site measurement requirements of the integrated circuit test system, this paper designs the DC parameter calibration module of the digital integrated circuit test system based on STM32 single-chip microcomputer as the core control, studies the methods of precision improvement based on multiple groups of devices, noise control, and error compensation, reduce the volume of the device, simplifies the measurement loop in the calibration process, and improves the DC parameter calibration accuracy of the digital channel of the integrated circuit test system, improve the portability and ease of use of the calibration device, and lay the foundation for the calibration device of the new generation integrated circuit test system.

Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model

The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel method to generate patterns that trigger Trojans without altering the circuit model. The generated patterns’ ability to diagnose clustered Trojans are also analyzed. The proposed method uses only single fault simulation to detect clustered Trojans, thereby reducing the computational complexity. Experimental results show that the proposed algorithm has a detection ratio of 99.99% when applied on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits. Experiments on clustered Trojans indicate a 46% and 34% improvement in accuracy and resolution compared to a standard Automatic Test Pattern Generator (ATPG)Tool.

Transmission Lines in Capacitance Measurement Systems: An Investigation of Receiver Structures.

Dielectric sensing based on capacitive measurement technology is a favourable measurement approach in many industries and fields of application. From an electrical point of view, a coupling capacitance must be measured in the presence of stray capacitances. Different receiver circuit structures have been proposed for the underlying displacement current measurement. Ideally, the sensor assembly is directly connected to the sensor circuitry to minimize the influence with respect to these parasitic capacitances. However, under harsh operating conditions, e.g., at high temperatures, the sensor and the receiver circuit must be separated in order to protect the electronics. Consequently, the receiver circuit and the sensor have to be connected by cables, e.g., coaxial cables. The measurement setup differs significantly from the ideal design with a direct connection. In this paper, we investigate the behaviour of three common measurement circuits for capacitive measurements in instrumentations with cables. We study the interaction between the sensor and the electronics and analyse the operating behaviour of the circuit, as well as the operating states of the amplifiers used. We also address cross-sensitivities in the sensor design due to stray capacitances. The analyses are carried out for different cable lengths and measuring frequencies, and conditions for the usability of the circuit are deduced. In addition to the operational behaviour, we also evaluate the circuits by means of a noise analyses. Based on this analysis, we show a direct comparison of the circuits. The analysis is based on simulation studies, as well as collaborative measurements on test circuits where all circuit parameters are provided. The test circuits are realized with dedicated state-of-the-art circuit elements and, together with the analysis approach and the results, thus provide a basis for future developments.

Design and analysis of a hybrid magnetic shielding system: application for the magnetic non-destructive testing of circuits

A magnetic shielding system combining three-axis active magnetic shielding and a high-Tc superconducting ring (TASR) was developed. The active shield mainly responds to DC field while the ring operates for shielding AC fields below 1 kHz. In this study, the system’s shielding effects were evaluated experimentally, and the results suggest that this system can effectively shield the interference of static and low-frequency magnetic fields to ensure the operation of high-precision magnetic sensors. The shielding factor reached 99.9% for geomagnetic field (DC, 38 500 nT), which exceeded 98% for about 10 000 nT AC magnetic field at 30–1000 Hz. Then, magnetic non-destructive testing of the circuit was performed in this TASR shielding system. The images clearly showed the magnetic field distribution in different kinds of circuits that could be inverted to current density information, indicating that the shielding system can detect circuit defects and has great application potential in integrated circuit diagnosis.

Dynamic Model of Medium Voltage Vacuum Circuit Breaker and Induction Motor for Switching Transients Simulation Using Clark Transformation

A derivation of the dynamic model of a medium voltage vacuum circuit breaker and induction motor in space vectors in coordinates αβ0 allow us to model switching transients in various dynamic states of the motor. In the case of the Clark transformation, the corresponding numerical integration technique can be selected including variable time-step integration techniques to avoid numerical instabilities due to the stiffness of the system. Assymetrical operations such as switching cause the power system to become unbalanced and the transformed equations α, β, and 0 are not uncoupled. Therefore, it is necessary to derive a coupling matrix between circuit breaker voltages and currents in the coordinate system αβ0. The subject of our interest is switching overvoltages that arise when turning off small inductive currents by a vacuum circuit breaker. When deriving the model of a vacuum circuit breaker, all its properties encountered during this action are taken into account, i.e., current chop, virtual current chop, dielectric barrier in the circuit breaker and its recovery rate, and the ability of the vacuum circuit breaker to extinguish high frequency currents. Simulation results are compared with the measured results on a medium voltage motor as well as with the simulation results of the mathematical model of the test circuit according to IEC 62271-110 resolved using the nodal method (EMTP algorithm). Models are implemented in the MATLAB/Simulink programming environment.

An Approach towards Designing Logic Locking Using Shape-Perpendicular Magnetic Anisotropy-Double Layer MTJ

In recent years, discovering various vulnerabilities in the IC supply chain has raised security concerns in electronic systems. Recent research has proposed numerous attack and defense mechanisms involving various nanoelectronic devices. Spintronic devices are a viable choice among various nanoelectronic devices because of their non-volatility, ease of fabrication with a silicon substrate, randomization in space and time, etc. This work uses a shape-perpendicular magnetic anisotropy-double oxide layer magnetic tunnel junction (s-PMA DMTJ) to construct a potential logic-locking (LL) defensive mechanism. s-PMA DMTJs can be used for more realistic novel solutions of secure hardware design due to their improved thermal stability and area efficiency compared to traditional MTJs. The LL system’s critical design range and viability are investigated in this work and compared with other two-terminal MTJ designs using various circuit analysis techniques, such as Monte Carlo simulations, eye diagram analysis, transient measurement, and parametric simulations. Hamming Distance of 25%, and output corruption coverage of 100% are achieved in the investigated test circuit.

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

The smartphone and low-cost microcontroller as an AC circuit study kit for high school

This article presents a smartphone and a low-cost microcontroller-based AC circuit educational module focusing on the measurements of alternating voltage, frequency, and phase shift as well as learning about a phasor diagram. A smartphone provides a signal generator as a signal source, the ESP32 microcontroller works for signal acquisition and the beadboard RC series circuit is a test circuit. In-house developed software, based on Microsoft Visual Basic (VB), was used for monitoring the input signal like an oscilloscope. The measured frequency and phase shift agree with the results obtained from the commercial oscilloscope benchtop. This developed module is an apparatus that may be useful in online learning situations with the home experiment during the pandemic situation and used in high school that lacks the instruments, i.e., function generator and oscilloscope.

Production and testing of the powerboard for ATLAS ITk Strip barrel modules

The upgrade of the ATLAS ITk strips detector for HL-LHC will employ a custom PCB (powerboard) for on-module DC-DC conversion, HV switching, and monitoring. Production of about 14100 of such PCBs with high reliability is a big challenge. This paper will present the production procedure and quality control (QC) testing system for the powerboards to be installed on ITk Strip barrel modules. During production, about 150 powerboards will be produced every week. Each powerboard will need to pass QC tests before they are assembled to module. The QC tests include thermal cycling between −35 °C and 40 °C, soak test (continuous running of DC-DC converter at high load at 20 °C), and basic functionality and characterization electrical tests of the low voltage (LV), high voltage (HV), and monitoring functions of the powerboard. A custom QC test system is described, which is based on a reusable PCB (active board) with all testing circuits, a one-time powerboard carrier card, and a Z-turn SoC board which hosts and runs the testing program. The production procedure and QC test system has been tested with 400 powerboards during pre-production, and the system has been proven ready for production with the desired testing program, speed, safety, and cost. Performance and typical failures of powerboards observed during the QC test of pre-production powerboards is also presented.

Research and Development of Intelligent Drying Detection Technology for Machine-Made Sand

This paper aims to develop a high precision variable dielectric constant capacitor detector for mechanical sand water content testing. The non-contact on-line test method can effectively solve the problems of low repeatability of test data, large hysteresis error and poor linearity due to the non-uniform water content. In terms of hardware, CAV444 is a high-precision integrated chip, which matches the corresponding test circuit. The system communicates with PC through serial interface and implements the man-machine interface of PC system based on VS. Secondly, the distribution map method is used to measure the water content of machine-made sand, and the error analysis is carried out. The test shows that the output of the capacitive hygrometer is 0-5 V. The delay time should not exceed 0.15%. The repetition rate was within 0.33%. The measurement accuracy of this method is less than 3.52%.

Active De-Excitation System Using Magnetically Coupled Secondary Coil and Charged Capacitor for Fault Protection of Superconducting Coils

Coils excited for high magnetic fields have large discharging time constants owing to high inductance and low resistance for large operating currents. This type of coil requires a de-excitation system to reduce the current as quickly as possible when a fault occurs and to minimize the damage caused by Ohmic heating. This paper introduces a new de-excitation system that rapidly reduces the current discharged through the dump resistor by using the active current of the secondary coil. To verify the performance of the proposed method, a de-excitation system utilizing the primary superconducting coil and secondary copper coil was constructed and discharging tests were performed. Good agreement was obtained between the circuit simulation and test results. The performance of the proposed system was compared with those of other de-excitation systems, and it was confirmed that the proposed approach provides a feasible and powerful means of reducing the fault energy load and that it reduces this load more than the other systems considered. In addition, the effects of the charging voltage, coupling coefficient, capacitor bank configuration, and diode on the performance of the de-excitation system were analyzed and information about the secondary section that most effectively reduces the current was obtained.

Evaluation and Suppression Method of Turn-Off Current Spike for SiC/Si Hybrid Switch

SiC MOSFET/Si IGBT (SiC/Si) hybrid switch usually selects the gate control pattern that SiC MOSFET turns on earlier and turns off later than Si IGBT, with the aim of making the hybrid switch show excellent switching characteristics of SiC MOSFET and reduce switching loss. However, when SiC MOSFET turns off, the fast slew rate of drain source voltage causes the current spike in Si IGBT due to the effects of parasitic capacitance charging and carrier recombination, which will produce additional turn-off loss, thus affecting the overall efficiency and temperature rise of the converter. Based on the double pulse test circuit of SiC/Si hybrid switch, the mathematical model of the turn-off transient process is established. The effects of the remnant carrier recombination degree of Si IGBT, the turn-off speed of SiC MOSFET and the working conditions on the turn-off current spike of hybrid switch are evaluated. Although adjusting these parameters can reduce the turn-off current spike somewhat, additional losses will be introduced. Therefore, a new method to suppress the turn-off current spike is proposed to balance the power loss and current stress.