Test Circuit Research Articles

Composite fault diagnosis of analog circuit system using chaotic game optimization-assisted deep ELM-AE

When multiple electronic components in an analog circuit fail simultaneously, since its high complexity, it is arduous to establish an accurate fault model and diagnose the composite faults precisely. Traditional approach for composite fault diagnosis is severely constrained since it excessively relies on domain expertise and signal processing technology. The rapid development of deep learning provides a new idea for it. In this study, an improved strategy based on deep extreme learning machine with autoencoder (DELM-AE) is proposed, which possesses more prominent capability on feature extraction and representation. The proposed method first utilizes multiple extreme learning machine with autoencoder (ELM-AE) to adaptively extract the hidden features from original collected signals layer by layer, which does not need to design representative features manually. Subsequently, efficient classification will be conducted based on extreme learning machine algorithm. All parameter values of the proposed network are determined at one time, eliminating the iterative updating process. To further enhance the performance of DELM-AE on feature extraction and classification, a novel chaos game optimization algorithm (CGO) is introduced to optimize the initial network parameters. The experimental results on two typical test circuits demonstrate that the proposed method, CGO-DELM-AE, can effectively diagnose the composite faults of analog circuit.

Safety analysis of 2-pin capacitor as 4-pin capacitor with frequency response

This paper presents an experiment to verify the safety effect of resolving an open capacitor failure by 4-pin capacitor structures or 2-pin capacitor structures by cut the copper pattern of the printed circuit board (PCB). Both solutions to the problem of open capacitor failure do not affect the next part of the circuit or devices in the operating frequency range of 100 kHz to 500 kHz. This research analyses the effect of using a 2-pin capacitor by cutoff the printed circuit board. The results of parallel patterns of copper stripes were analyzed at different stages and frequency responses analysis in the range of 100 kHz to 4.50 GHz based on a frequency response analysis (FRA), which are experimental results of insertion loss (S21) and return loss (S11). Using a conventional capacitor instead of a 4-pin capacitor of RT2010 type did not show any harmful effects from self-oscillation within the circuit or from the external circuit. The accuracy was verified by simulating the computer program and measuring the test circuit.

An optimized parameter design method of SiC/Si hybrid switch considering turn-off current spike

In order to reduce the switching loss of SiC MOSFET/Si IGBT (SiC/Si) hybrid switch, the switching mode that turn off the Si IGBT prior to the SiC MOSFET is generally adopted to achieved the zero-voltage switching operation of IGBT. The minority carrier in N-base region of the IGBT are recombined in the form of exponential attenuation due to the conductivity modulation effect. When the SiC MOSFET is turned off, if the carrier recombination process of the IGBT is not finished, it needs to bear a large collector–emitter voltage change rate, resulting in apparent current spike. This current spike will increase the current stress of the device and produce additional turn-off loss. The equivalent model of double pulse test circuit of SiC/Si hybrid switch considering parasitic parameters is established, and the turn-off transient process is given analytically. The influence of turn-off delay time, circuit parameters and working conditions on current spike are analysed quantitatively. Combined with the consideration of device stress and comprehensive turn-off loss, an optimized circuit design method of SiC/Si hybrid switch considering turn-off current peak is proposed, which provides theoretical and design guidance for high reliability and high efficiency SiC/Si-based converters.

Solving EMC problems in the design of new HV test laboratory

The paper deals with solving electromagnetic compatibility (EMC) problems in the design of a new, case study, industrial high voltage test laboratory, intended to be used for testing of transformers and other apparatus up to 550 kV rated voltage. Modern high voltage test facilities are equipped, apart from primary test devices like AC, DC and impulse voltage generators etc., also with sophisticated numerical measuring instruments and informatics technology. Since such devices are sensitive to transient overvoltages, the highest degree of EMC is to be secured. This can be achieved by proper earthing and screening of test laboratory, what shall be designed in a way to satisfy all requirements conditioned by building lightning protection, personal protection and system earthing, avoiding electromagnetic compatibility disturbances at the same time. One of the main tasks is solving electromagnetic compatibility problems caused by outdoor electromagnetic disturbances originating from various unknown sources. Those disturbances and interferences may seriously influence measuring accuracy and readings of test devices, what consequently leads to false results. The stated is especially relating to partial discharge measurements. As to avoid such disturbances, the laboratory shall be completely screened with a net forming optimally designed Faraday cage. On the other hand, at high voltage tests with impulse voltages, especially with chopped tail waves, steep transient overvoltages may be generated. As a consequence, high transient potential differences between particular points along the earth electrode may occur, what can even lead to flashovers between parts of it. Therefore is of utmost importance to provide proper earthing and low inductance current return path for impulse high voltage test equipment where high frequency transients are to be anticipated. Improper earthing and bonding may result, apart from mentioned flashovers, in severe induced voltages in secondary cables with consequential influence on test results, possible destruction of measuring instruments and hazardous touch voltages for personnel. For analyzing transient potential differences, it is important to model, with maximum accuracy, impulse test circuit (impulse generator, chopping spark gap, voltage divider, Faraday cage, fundament earth electrode, earthing strips, earthing rods etc.). Magnitude of transient potential difference between particular points is proportional to earth electrode inductance, i.e. low inductance of earth electrode will result in decrease of transient potential difference.

A new fault-tolerant single-bit comparator in QCA technology using a novel X-NOR gate

Quantum-dot Cellular Automata (QCA) is one of the potential remedies to the limitations of transistor-based technologies. The QCA is brand-new, significant nanotechnology that has caught the attention of many scholars. It has a lot of tempting qualities, such as quick speed, low energy usage, and small size. This work uses QCA's cell contact rules to provide a new fault-tolerant XNOR gate. Additionally, a unique comparator circuit is suggested that makes use of the fault-tolerant XNOR gates. The proposed comparator offers a noteworthy improvement in both area and gate count. The proposed circuits' functionality, implementation, and testing are validated using the QCADesigner simulator. Only 106 cells make up this fault-tolerant comparator, which has a desirable size of 0.10 µm2. Additionally, the outcomes showed that the design offers improved fault-tolerant features in comparison to its alternatives. Investigations also looked into single-cell omission, displacement, misalignment, and other deposition defects. Based on the experiment's outcomes, the suggested comparator can tolerate more than 80 % of faults.

Research on large-capacity impulse test technology for distribution transformer based on energy storage intelligent power

Large-capacity impulse test of distribution transformer requires a large amount of instantaneous energy, while the impulse mode of conventional dedicated high-voltage line and generator requires synchronous switch, adjusted impedance, generator, etc., which has low operability and the risk of affecting system stability. To solve the problems in the large-capacity impulse test of distribution transformers, this paper proposes a high-current impulse test method based on energy storage technology, power electronics technology and intelligent control technology. The stepless continuous adjustable voltage of large capacity short circuit test, precise control of test current peak factor and stable output are realized, and the corresponding smart energy storage power supply for the large capacity test of a distribution transformer is developed. Through simulation and live test, the design of the energy storage intelligent power supply proposed in this paper greatly reduces the power supply side capacity requirements of large capacity impulse test of power distribution, and has excellent operability in field test.

Design and application of short circuit test scheme for Hu Zhou DPFC project

The short circuit test of distributed power flow controller (DPFC) is still a blank in the world. In order to test the effectiveness and adaptability of DPFC in case of line failure, it is necessary to carry out short circuit tests in DPFC projects. Based on the Hu Zhou DPFC Project, this paper proposes the control and protect strategy of DPFC which is coordinated with the protect strategy of AC line, designs single phase short circuit grounding test scheme of the AC line where DPFC is located. In the application, the action logic of DPFC under single-phase grounding fault is verified, the single phase short circuit test of DPFC were completed for the first time, and the transient voltage and current were obtained. It provides technical support for the popularization and application of DPFC project.

A built-in self-test and self-adjustment method of MEMS pressure sensor

MEMS device degradation due to aging and other factors is becoming a major concern because it will cause parametric deviations and catastrophic failures in the mechanical and structural subsystems. However, MEMS testing in general which needs specific sophisticated testing equipment is complicated and time-consuming. To solve these problems, this paper specifically introduces a built-in self-test method which based on the periodic observation of the temperature-dependent output signal. A packaging scheme is designed and the test circuit is built to conduct test experiments on MEMS pressure sensors with different ranges and materials. The experimental results show that this method can effectively test the performance and will not affect the continued normal operation of the sensor. Furthermore, some compensation is made to correct the output to greatly improve the accuracy and reliability. Low cost, ease of implementation, and possibility to monitor in real time are the main advantages.

Multifunctional intelligent line-following robot

This paper introduces an intelligent robot with the functions of automatic line patrol, positioning and parking, real-time ranging, color recognition and object block transmission. The H bridge drive motor is controlled by Arduino as MCU, so that the intelligent car can realize the functions of forward, backward and steering. The circuit test, hardware debugging, PCB drawing, code improvement and overall structure design in the design process are described in the article. The conclusion is that the robot can realize normal line patrol, parking, ranging, color recognition and block delivery.

Self-Coupling and Mutual Pulling in Phase-Locked Loops

The influence of coupling of oscillators in phase-locked loops (PLLs) was studied here. Particularly, numerical analyses based on nonlinear differential equations of the self- and mutual coupling systems were performed and compared with the results of the linear approximation model under synchronous conditions. The analysis revealed that coupling using the reference clock caused greater PLL instability than that caused by self-coupling for a given coupling strength. This shows that the phase error of mutual coupling exhibits the same behavior as that of reference-clock coupling in the single PLL under synchronous conditions, and the noise sensitivity of mutual coupling is twice that of the reference-clock coupling. In addition, the phase error of mutual coupling in the quasi-synchronous condition strongly depends on the relationship between the frequency difference of the two PLLs and the PLL bandwidth. We designed and fabricated the test circuits for theoretical verification using the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> standard CMOS process. From the measurements, adjustment of the timing difference between the two PLLs is effective in mitigating mutual coupling under synchronous conditions. Moreover, we implemented mutual injections between two oscillators in the test circuit and confirmed their effectiveness. The proposed methods will be useful for achieving the compact and effective cancellation of the mutual coupling between PLLs.

A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process

This study investigated the use of a built-in-self-test (BIST) module detecting catastrophic errors in photon-counter accumulator for liquid contamination level measurement. Efficient algorithms are exceptionally demanded for a high-count rate and low voltage system photon counting circuit on-chip. The photon counter sensors are also required high sensitivity digital counter that encodes the arrival of photon in precise timing to prevent any count erroring the absence of light. The proposed BIST is integrated on the data acquisition system, where the accumulator is located. The design circuit, functionality and topology tests of BIST and circuit under test are realized with 180 nm Silterra CMOS Process. The same Verilog codes are verified using field programmable gate array (FPGA) to predict the hardware functionality prior fabrication. The measurement was able to detect at least 90 % fault coverage within 16-bit data acquisition system at minimum operating frequency of 166.7 MHz.

A High-Detection-Efficiency Optoelectronic Device for Trace Cadmium Detection.

Cadmium (Cd) pollution in soil is a serious threat to food security and human health, while, currently, the most widely used detection methods cannot accurately reflect the content of heavy metals in soil. Soil heavy metal detection combined with microelectronic sensors has become an important means of environmental heavy metal pollution prevention and control. X-ray Fluorescence spectrometry (XRF) can capture the excitation spectrum of metal elements, which is often used to detect Cd (II). However, due to the lack of high-performance optoelectronic devices, the analysis accuracy of the system cannot meet the requirements. Therefore, this study proposes a high-detection-efficiency photodiode (HDEPD) which can effectively improve the detection accuracy of the analyzer. The HDEPD is manufactured based on a 0.18 μm standard complementary metal-oxide-semiconductor (CMOS) process. The volt-ampere curve, spectral response and noise characteristics of the device are obtained by constructing a test circuit combined with a spectral detection system. The test results show that the threshold voltage of HDEPD is 12.15 V. When the excess bias voltage increases from 1 V to 3 V, the spectral response peak of the device appears at 500 nm, and the photon detection probability (PDP) increases from 41.7% to 52.8%. The dark count rate (DCR) is 31.9 Hz/μm2 at a 3 V excess bias voltage. Since the excitation spectrum peak of Cd (II) is between 500 nm and 600 nm, the wavelength response range of HDEPD fully meets the detection requirements of Cd (II).

Development of a Stretchable Circuit and its Integration Method on Knit Fabrics for Lower Back Injury Prevention

Advancements in wearable technology and smart textiles have also opened new possibilities in the sports and medical fields. One of the examples of a relevant application case can be found in cycling. This paper expands on previous research on stretchable electronics on knit fabrics. It describes the development of stretchable circuits for the lower back position and motion tracking to prevent back pain in recreational (road) cyclists by combining electrical and textile engineering with insights generated in rehabilitation sciences and sports physiotherapy. The research process included developing and testing of the functional circuit integrated into a cycling jersey. Thermoplastic polyurethane films were used for the textile integration process to achieve maximum comfort and after-life disassembly possibility. Reliability tests, e.g. washing (ISO 6330-2012) and tensile tests, were conducted. It is concluded that while mechanical stress during washing cycles remains a serious concern for reliability and durability, the use of water-repellent thermoplastic polyurethane sealing seriously reduces the damage caused by water and detergents.

An efficient, safe, and energy-saving saddle for pressure vessel based on electro-permanent magnet technology

In this paper, a novel magnetic transport saddle based on the electro-permanent magnet (EPM) technology is proposed. A strong and stable magnetic force can be generated by passing only a momentary current during loading and unloading since the magnetic force is provided by the internal permanent magnet, not the electromagnet. The EPM system is convenient to control and has low energy consumption. This research commenced with a preliminary design of the magnetic circuit structure and circuit structure. The feasibility of this magnetic circuit structure is verified by theoretical derivation and magnetic field simulation, and the factors influencing the magnetic force are further investigated. Subsequently, transient thermal analysis was performed for the extreme case of continuous magnetization and demagnetization. Then, a series of experiments such as electrical circuit, magnetic field, and tensile test were performed for the EPM chuck. Based on the magnetic element, the magnetic transport saddle is designed and the magnetic field simulation is performed for the magnetization state. In addition, when the wall thickness of the transport cylinder is too thin and the magnetic force is insufficient, this paper proposes a solution to increase the cushions inside the transported equipment. Finally, the energy-saving performance of the magnetic transport saddle based on the EPM technology is calculated.

Study on Corrosion Behavior of Simulated Welding Microstructure of Austenitic Stainless Steel

In this paper, the simulated welding structure of austenitic stainless steel is prepared by external heating, and the corrosion resistance of austenitic stainless steel in different areas of heat affected zone (HAZ) is evaluated by means of metallographic structure analysis, electrochemical impedance spectroscopy (EIS) test and equivalent circuit numerical fitting analysis. The result shows that the simulated welding structure of austenitic stainless steel had a growth trend with the increase of heating temperature, but the growth trend is not very obvious. The short thermal process has insufficient driving force for the growth of single-phase austenitic structure. The resulting of product resistance and charge transfer resistance of simulated welding microstructure of austenitic stainless steel is not completely consistent. The simulated welding microstructure of stainless steel shows the tendency of corrosion resistance degradation with the heating temperature increasing, and it has slightly lower when the maximum heating temperature locating at 1000-1100 °C.

Assessment of knowledge integration in student learning of simple electric circuits

A concept test for simple electric circuits is effective in identifying features of knowledge integration, including context dependence and fragmentation of knowledge components, memorization-based problem solving, difficulty in transfer to novel contexts, and lack of meaningful connections between microscopic and macroscopic models of electric current.

Switching Characteristic Analysis and Application Assessment of SiC MOSFET With Common Source Inductance and Kelvin Source Connection

SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s with packages of common source inductance (TO-247-3) and kelvin source connection (TO-247-4) are both widely used devices in the existing power conversion. Transient analysis of switching characteristics reveals some evaluation mistakes and misguidance design by using the conventional test circuit due to the difference packages. However, the more precise gate characteristic of TO-247-3 SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> can be obtained by using TO-247-4 device package. Based on the unique feature, this article provides an improved evaluation method to get a comprehensive comparison of TO-247-3 and TO-247-4 SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> commutation as the active and passive switch devices in the typical half-bridge circuit. The results indicate that 4-PIN SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> has both advantages of low switching loss and reduced d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t.</i> Furthermore, this article first reveals that the widely used drive design for TO-247-3 <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> with active miller clamped drive IC has a potential irrational circuit defect. Mathematical model analysis and experiment test have been accomplished to verify the superiority of the improved evaluation method. TO-247-4 SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> is more promising in application of high efficiency, high frequency as well as strict EMI requirement.

High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor

High Accuracy Test Techniques with Fine Pattern Generator and Ramp Test Circuit for CMOS Image Sensor

사물인터넷(IoT)를 이용하여 시간과 공간적 제약 없이 원격 제어 가능한 전동 창호 시스템 개발 연구

The house we live in and the window system of the house have the purpose of protecting users from the natural environment. Protecting oneself from others according to the social change of the increase in single-person households, In order to meet the needs of users for convenience and quality of life improvement, there is a demand for an electric window system that responds to an emergency situation of indoor air quality improvement and harmful gas leakage in an indoor environment. In this study, we propose a function that enables the user to remotely control the window system without spatial and temporal restrictions by realizing the automatic opening and closing function of the window system in the house using IoT remotely even in emergency situations and normal times. To make it feasible, the field applicability of the proposed system was presented through circuit configuration, design, manufacturing, and testing. The proposed system is characterized in that the size of the proposed system is reduced to be applied to the actual field, and A/S convenience is also considered by applying a linear transfer module to increase the ease of installation. In the future, it is thought that additional research is needed to release it as a standardized product to increase the possibility of actual field application.

A SiC-Based Liquid-Cooled Electric Vehicle Traction Inverter Operating at High Ambient Temperature

This paper describes the design process of a high-power-density 100 kW (34 kW/L) traction inverter for electric vehicles, operating at an ambient temperature of 105 °C. A detailed thermal analysis is performed based on the thermal behavior of the switching devices, and the results are used to estimate the semiconductor device junction temperature and to determine the requirements of the cooling system to achieve the target power level. A high-temperature gate drive board aiming for reliable system operation in electric vehicles is developed. An overcurrent protection scheme based on parasitic inductance between the power source and the Kelvin source of the power module has been implemented. A dc-link decoupling snubber circuit is designed numerically based on a detailed forth-order high-frequency equivalent circuit of a double pulse test circuit. The approach to optimize the snubber circuit, not only for the voltage spike suppression but also for good thermal performance, is proposed. Finally, a hardware prototype with SiC power modules has been built and tested at 60 kW continuous power and 100 kW for 20 seconds at 105 °C ambient temperature and 65 °C inlet coolant temperature.