Capacitor Test Research Articles

Limiting Native Oxide Regrowth for High-k Gate Dielectrics

AbstractA cleaning process resulting in atomically smooth, hydrogen-terminated, silicon surface that would inhibit formation of native silicon oxide is needed for high-k gate dielectric deposition. Various cleaning methods thus need to be tested in terms of resistance to native oxide formation. Native oxide re-growth is studied as a function of exposure time to atmospheric ambient using ellipsometry. Hafnium dioxide film (k ~23) is deposited on the as-cleaned substrates by electron beam evaporation and subsequently annealed in hydrogen. The difference in the effective oxide thickness re-grown on surfaces treated with the conventional RCA and modified Shiraki cleaning methods, after one-hour exposure, can be as large as 2 Å. This is significant in device applications demanding equivalent oxide thickness less than 20 Å. The degree of hydrogen passivation, surface micro-roughness and organic removal capability are considered to be the main factors that explain the differences between the cleaning methods. Data derived from capacitance-voltage analysis of test capacitors verified the trend observed in the native oxide thickness measurements. An increase of 10~15 % in accumulation capacitance is observed in the samples treated by the new cleaning method.

Single-shot, repetitive, and lifetime high-voltage testing of capacitors

Four different types of capacitors have been tested to determine the maximum usable high voltage. Ceramic, drop-dipped film, molded-mylar tubulars, and polyester/foil capacitors of different values and different nominal voltages were tested in four modes: the single-shot mode, the repetitive mode, the lifetime dc voltage mode, and the group mode. Experiments have shown that the breakdown voltage for all types of the capacitors tested is ten to seventeen times higher than the nominal voltage. The energy stored in the capacitors for a short time under overstress conditions is from 100 to 250 times higher their normal energy. Data are given for the limitations for single capacitors, and for two, three, and four capacitors connected in parallel.

Copper drift in methyl-doped silicon oxide film

Drift of copper (Cu) ions into methyl-doped silicon oxide film, a promising low-dielectric-constant (low-κ) material for inter-layer dielectrics applications in ultralarge scale integrated circuit (ULSI) interconnects, was investigated using bias temperature stressing (BTS)/capacitance–voltage (C–V), current–voltage (I–V) at elevated temperatures and time-dependent dielectrics breakdown (TDDB) tests. Standard and control metal–insulator–semiconductor capacitor test samples with “sandwich” dielectric layer structures were used in the tests. BTS in nitrogen (N2) ambient at an electric field magnitude up to 1.5 MV/cm and with temperatures between 175 and 275 °C was used to accelerate the Cu ion drift. By studying flat band voltage shift in C–V tests, leakage current magnitude in I–V tests and time to fail in TDDB tests, it is demonstrated that Cu ions readily drift into methyl-doped silicon oxide under electric fields at elevated temperatures. Results obtained using different techniques correlate well to each other. The activation energy of Cu drift is determined to be 0.76 eV in N2 ambient. The film is found to have poorer resistance to Cu drift than silicon oxide (SiO2) deposited using plasma-enhanced chemical vapor deposition (PECVD). Therefore, good Cu drift barrier layers are required for reliable ULSI interconnects using this low-κ material. A thin layer of PECVD SiC is proven to be a good Cu drift barrier layer.

Electrical and spectroscopic comparison of HfO2/Si interfaces on nitrided and un-nitrided Si(100)

The interfacial chemistry of the high-k dielectric HfO2 has been investigated on nitrided and un-nitrided Si(100) using x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). The samples are prepared by sputter depositing Hf metal and subsequently oxidizing it. A 600 °C densification anneal is critical to completing Hf oxidation. These spectroscopic data complement electrical testing of metal oxide semiconductor capacitors fabricated with ∼50 Å HfO2 on nitrided and un-nitrided Si(100). Capacitors with interfacial nitride show reduced leakage current by a factor of 100 at a −1 V bias. Concurrently, interfacial nitride increased capacitance 12% at saturation. XPS shows that an interfacial layer composed of nonstoichiometric hafnium silicate (HfSixOy), forms at both the HfO2/Si and HfO2/SiNx interfaces. Differences in the Si 2p and O 1s XP spectra suggest more silicate forms at the un-nitrided interface. HfO2 films on un-nitrided Si show more O 1s and Si 2p photoemission intensity characteristic of HfSixOy. SIMS depth profiles through the buried interface are consistent with interfacial silicate formation, as shown by a HfSiO+ ion signal, that is sandwiched between HfO2 and SiNx. SiNx is suggested to minimize interfacial HfSixOy formation by limiting the amount of Si available to interact with the HfO2 layer.

High temperature reliability testing of aluminum and tantalum electrolytic capacitors

Nowadays, many innovations in the automobile are enabled by electronics. Ambient requirements can be very stringent especially when the temperature reaches 150 °C or even more. Especially electrolytic capacitors are known to be critical devices at high temperatures. Therefore, it is necessary to validate the performance of such components and check their reliability during high temperature operation. In this paper we discuss how to predict the lifetime of both aluminum and tantalum electrolytic capacitors. In that aim we first review state of the art qualification tests that allow a life prediction. We describe a test setup that we have built in order to investigate electrolytic capacitors by LCR and leakage current measurements at temperatures above current manufacturer's specifications. Results for different capacitors after variation of tests conditions will be presented.

Model Relating Thin Film Pzt Crystallographic Texture to Ferroelectric Switching Performance

AbstractThe fundamental physical property used for data storage in a ferroelectric non-volatile memory (FRAM) is the remanent polarization of a ferroelectric capacitor. In order to sense the data state of the capacitor, the charge pulse generated by either a switching or non-switching ferroelectric polarization is detected. Since the polarization of the ferroelectric is a vector property, the switchable polarization response of a ferroelectric capacitor is necessarily dependent on the texture of the ferroelectric material used to make the capacitor. A series of Ca, Sr, and La doped PbZr0.4Ti0.6O3 (PZT) capacitor test samples were produced with texture ranging from nearly complete {111} texture to random orientation. The volume fraction of the textured material was quantified by X-ray diffraction. An experimental correlation between texture and the switchable polarization was established using pulse switching measurements. A mathematical model was developed to explain the dependence of the switchable polarization on the crystallographic texture. It was found that the dependence of the saturated switchable polarization on texture required that there was no 90° domain reorientation. The impact of these findings will be related to the performance of FRAM.

Contactless testing of wiring networks by an electron beam system utilizing induced current detection

Flying-probe mechanical test systems which detect opens and shorts in electrical networks within a multichip module substrate by measuring the capacitance of network elements have found application within the manufacturing industry. The feasibility of a contactless capacitance measurement method using an electron beam is reported here. Compared to mechanical probers, an electron beam capacitance tester could have higher throughput, test smaller features, and eliminate the possibility of probe damage to substrates. The test method is easily implemented as it employs a low voltage probe beam with a small deflection range, electron flood guns, a grid or electrode above the substrate, and an induced current detector. The capacitance between the node under test and the conductive plane is measured (indirectly) as the node is charged by the probe beam. Capacitance measurement to the accuracy required to detect opens and shorts has been demonstrated.

Characteristics of ferroelectric Pb(Zr,Ti)O3 thin films having Pt/PtOx electrode barriers

We have investigated the feasibility of the Pt/PtOx multilayer as an electrode barrier for Pb(Zr,Ti)O3 (PZT)-based ferroelectric random access memories. PtOx and Pt layers were prepared on polycrystalline-Si/SiO2/Si substrates by means of the sputtering method in Ar and O2 ambience, and the Pb(Zr0.53Ti0.47)O3 layer was prepared by the sol-gel method. A capacitor consisting of Pt/PtOx/PZT/PtOx/Pt/PtOx/poly-Si had a remanent polarization of 18 μC/cm2 and a low coercive field of 32 kV/cm. The polarization fatigue behavior of test capacitors was improved as compared with that of Pt/PZT/Pt, which showed negligible fatigue loss of 15% after 1011 switching repetitions with a frequency of 1 MHz.

Nondestructive testing of ceramic capacitors by partial discharge method

The majority of ceramic capacitors are fabricated with BaTiO 3. Dielectric breakdown is one of the primary drawbacks for ceramic capacitors. In this research, instead of the destructive reliability tests of BaTiO 3 ceramic capacitors, a new nondestructive testing method was proposed. The BaTiO 3 ceramics used in this study were sintered at 1300°C, 1350°C, 1400°C or 1450°C to vary pore size distribution. Pore size of barium titanate ceramics increased with sintering temperature. The breakdown field and partial discharge inception field decreased with increase of sintering temperature. This means that the large pores in over-fired BaTiO 3, having relatively low inception voltage of partial discharge, decrease the breakdown field. Reliability of ceramic capacitors can be nondestructively evaluated by partial discharge testing method.

Ka-band InP high electron mobility transistor monolithic microwave integrated circuit reliability

The reliability of AlInAs/GaInAs high electron mobility transistor (HEMT) monolithic microwave integrated circuits on InP substrates from HRL Labs has been studied with elevated-temperature lifetests on Ka-band LNAs, as well as ramped-voltage tests on individual capacitors. In the lifetests the LNAs were put under normal DC bias, and aging was accelerated by heating to channel temperatures of 190°C and 210°C. Room-temperature characterizations involved DC tests of HEMT parameters as well as 30 GHz measurements of gain, noise figure and phase. Aging caused the noise figure to drop by a few tenths of a dB, and the phase changed by ±10°. The gain dropped gradually by several dB. Taking 1 dB drop in gain as the failure criterion, we find an activation energy of 1.1 eV, and a mean time to failure (MTTF) at an operating channel temperature of 70°C of 7×10 6 h. In the ramped-voltage tests, 10×10 μm 2 capacitors were taken to breakdown at two different temperatures, and several ramp rates. This yielded a voltage acceleration factor of γ=36–39 nm/V, and thermal activation energy of 0.11–0.13 eV. Next, ramped voltage tests were conducted on 200×200 μm 2 capacitors, typical of those in circuits. These were done at 25°C and 3.0 V/s only, and at least 1000 specimens were tested per wafer. The known acceleration factors were used to find the MTTFs at 70°C, with operating biases of 5 or 10 V. For the majority of the population the MTTFs are about 10 9 h, while only 0.07% of the population has MTTF less than 1×10 6 h. The combination of results from elevated-temperature lifetests and ramped-voltage capacitor tests indicates excellent reliability for this MMIC technology in terms of known “wearout” failure mechanisms.

Conduction properties of electrically erasable read only memory tunnel oxides under dynamic stress

The write and erase programmable operations in electrically erasable read only memories (EEPROM) which are based on Fowler–Nordheim tunneling injection through a thin tunnel oxide window have been reproduced on specific large area double polycrystalline (poly) test capacitors. These structures integrate the different stacked layers (upper control gate polysilicon layer; interpoly dielectric layer; floating gate polysilicon layer; tunnel oxide; N + substrate) of the active area of a memory cell state transistor. Stress pulses similar to those used in the programming memory cells were applied to the upper polysilicon layer. The variations of the tunnel oxide electrical conduction properties after numerous write-erase cycles were studied by measuring the current as a function of voltage characteristics of the structure. The Fowler–Nordheim constants were obtained as a function of the number of stress cycles. A model based on a simple equivalent electrical circuit was then implemented to simulate the resulting variations of the floating polysilicon gate charge and of the threshold voltage of the structure in both write and erase modes. These variations were compared to those directly measured on a memory cell. It is shown that the closure of the programmable window in memory devices can be unambiguously attributed to a decrease of the tunnel oxide conductivity.

Dielectric measurements for power electronic applications

Capacitors are utilized in a variety of different ways in power electronic circuits. Typical applications are in snubber, clamping, and resonant circuits. For design purposes, it is necessary to make an accurate measurement of the actual behavior of the capacitance that is added to the circuit under conditions related to those prevailing in a converter. For this purpose, a number of different measurement systems or techniques can be utilized. Four of these measurement systems are compared. These are small-signal variable-frequency measurement, large-signal quasi-DC measurement, in-situ high-voltage measurement and small-signal with large DC bias voltage measurement. Each of these measurement techniques returns characteristic values based on its particular model of the test capacitor. These tests are done on both ceramic and nonceramic capacitors at room temperature. The results are discussed.

New electrode-barrier structures for high density ferroelectric memories

In this paper, two electrode-barrier structures based on Pt-Rh and Pt-Ir alloys and their oxides are proposed for high-density ferroelectric memory applications. These electrode-barriers are multi-layered, comprising a diffusion barrier (PtRhOx or PtIrOx), metal alloy (PtRh or PtIr) and another PtRhOx or PtIrOx layer for fatigue reduction in the case of PZT capacitors. Both lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT) capacitors based on the electrode-barriers were used in the present study. The electrode-barrier structure acts as a conducting electrode as well as an excellent diffusion barrier for lead, bismuth, oxygen and silicon. The PZT test capacitors fabricated on these electrode-barriers showed excellent fatigue resistance with other ferroelectric properties being similar to those on Pt. Also, these electrode-barriers are stable, and remain conductive even up to the processing temperatures of SBT (750 °C). This makes direct integration of both PZT and SBT capacitors on to a poly-Si plug attainable. In addition, the conducting electrode-barrier structures can be deposited in situ, directly over n+polycrystalline Si, thereby significantly improving the density of the device.

Performance of ferroelectric based tunable capacitors as a function of electrode geometry

High quality Ba0.4Sr0.6TiO3 and SrTiO3 films were grown by Pulsed Laser Deposition on single crystal LaAlO3 and MgO substrates. Temperature dependencies of the dielectric constant and loss tangent of the films were studied using planar interdigitated test capacitors with various electrode geometries. The temperature where the maximum or “peak” capacitance occurs (Tp and referred to as the “peak temperature”) is found to depend on the electrode geometry in these films. As much as 40 K difference in Tp was observed between the STO test capacitors with 5 μm and 40 μm gaps between electrodes. Interface built-in electric field and metal-ferroelectric thermal mismatch strain are considered as possible explanation of the effect of electrode geometry on peak temperature of the capacitors.

Reliability of unencapsulated SMD plastic film capacitors

Small and low cost unencapsulated SMD plastic film capacitors were manufactured with different terminal metal compositions and dielectric materials. Capacitors made with a polyethylene naphthalate film dielectric were produced using a winding method. The terminals were metallized using the flame spraying process. The terminals of the test capacitors consisted of three different metal layers. The base metal layer, which was aluminum, was coated with brass or copper. The top layer was a sprayed lead‐free, tin‐based solder to ensure the solderability of the terminals. The reliability of the unencapsulated test capacitors was evaluated using standard temperature cycling, humidity storage, and high temperature environmental tests. Solderability and resistance to soldering heat were tested by mounting the test capacitors using the reflow soldering technique. The electrical properties including capacitance, insulation resistance, and dissipation factors at 1kHz and 100kHz were verified.

Low temperature processed 0.7SrBi2Ta2O9–0.3Bi3TaTiO9 thin films fabricated on multilayer electrode-barrier structure for high-density ferroelectric memories

Thin films of solid-solution material 0.7SrBi2Ta2O9–0.3Bi3TaTiO9 (0.7SBT–0.3BTT) were fabricated on n+-polycrystalline (n+-poly) Si substrates by a metalorganic solution deposition technique at a low processing temperature of 650 °C using a Pt–Rh/Pt–Rh–Ox electrode-barrier structure. The Pt–Rh/Pt–Rh–Ox structure was deposited using an in situ reactive radio frequency sputtering process. The electrodes had a smooth and fine-grained microstructure and were excellent diffusion barriers between the 0.7SBT–0.3BTT thin film and Si substrate. The ferroelectric (0.7SBT–0.3BTT) test capacitors using these electrode-barrier grown directly on Si showed good ferroelectric hysteresis properties, measured through n+-poly Si substrate, with 2Pr and Ec values of 11.5 μC/cm2 and 80 kV/cm, respectively, at an applied electric field of 200 kV/cm. The films exhibited good fatigue characteristics (<10% decay) under bipolar stressing up to 1011 switching cycles and the leakage current density was lower 10−7 A/cm2 at an applied electric field of 200 kV/cm. The good ferroelectric properties of 0.7SBT–0.3BTT solid-solution thin films at a low processing temperature of 650 °C and excellent electrode-diffusion barrier properties of a Pt–Rh/Pt–Rh–Ox structure are encouraging for the realization of high-density nonvolatile ferroelectric random access memories on silicon substrates.

Thermal dry oxidation of Si 1-x-yGe xC y strained layers grown on silicon

The incorporation of C into strained Si 1-xGe x to form partially compensated Si 1-x-yGe xC y layers improve their critical thickness and thermal stability against relaxation. Thus, these ternary alloys are attractive for the realization of MOS-gated HFETs with the gate grown by thermal oxidation. For this purpose, we present a detailed study of the growth kinetics of SiO 2 in the thin oxide regime for tensile and compressive layers. The oxides have been analyzed by FTIR. The modification of the Si 1-x-yGe xC y layers after oxidation has been studied by FTIR (substitutional carbon, β-SiC precipitation) and SIMS (Ge and C depth profiles). From these analyses, suitable process windows for dry thermal growth of oxides with good quality are defined. Preliminary results of the electrical characterization performed on test capacitors are shown.

Gel polymer electrolytes for electric double layer capacitors

Gel polymer electrolytes consisted of polyvinylpyrrolidone (PVP) and PVP–polyvinylacetate (PVP–PVAc) as base polymers, (C 2H 5) 4NBF 4 as an electrolyte salt and propylene carbonate (PC) as a plasticizer. The electric conductance of the gel polymer electrolytes, the capacitance and charge–discharge current efficiency of test capacitors with these electrolytes and activated carbon fiber were measured. The conductivity of the gel polymer electrolytes was measured in the range between −20 and +60°C, and was around 10 −3 S cm −1 at 25°C. The discharge capacitance of one of the electrode of model capacitors with PVP–PVAc-based polymer was 0.74 F cm −2 (38 F g −1), and cycling current efficiency was over 90%.

Breakdown of gate oxides during irradiation with heavy ions

Breakdown of thin gate oxides from heavy ions is investigated using capacitor test structures. Soft breakdown was observed for 45 /spl Aring/ oxides, but not for 75 /spl Aring/ oxides. Lower critical fields were observed when experiments were done with high fluences during each successive step. This implies that oxide defects play an important role in breakdown from heavy ions and that breakdown occurs more readily when an ion strike occurs close to a defect site. Critical fields for 75 /spl Aring/ oxides are low enough to allow gate rupture to occur at normal supply voltages for ions with high LET.

A reliability comparison of RTO and furnace thin SiO 2 layers: effect of the oxidation temperature

Three thermal oxidation methods aimed at growing thin SiO 2 films have been considered: Low temperature oxidation, O 2-diluted oxidation, and Rapid Thermal Oxidation (RTO). These procedures differ not only in their oxidation temperature but also in the thermal uniformity that is possible to achieve across the wafer. The electrical evaluation of the test capacitors show that longer times-to-breakdown are attained by the RTO samples for thicknesses down to 50 Å. The observed behaviour is explained in terms of the different mechanical stress levels in the different samples due to their different oxidation temperatures according to viscoelastic relaxation considerations and is further confirmed by the analysis of their FTIR spectra. Despite their better intrinsic breakdown features, RTO oxides exhibit more defect related failures that arise from wafer stress related problems due to the spatial thermal gradients that are characteristics of RTO operation.