Abstract
The incorporation of C into strained Si 1-xGe x to form partially compensated Si 1-x-yGe xC y layers improve their critical thickness and thermal stability against relaxation. Thus, these ternary alloys are attractive for the realization of MOS-gated HFETs with the gate grown by thermal oxidation. For this purpose, we present a detailed study of the growth kinetics of SiO 2 in the thin oxide regime for tensile and compressive layers. The oxides have been analyzed by FTIR. The modification of the Si 1-x-yGe xC y layers after oxidation has been studied by FTIR (substitutional carbon, β-SiC precipitation) and SIMS (Ge and C depth profiles). From these analyses, suitable process windows for dry thermal growth of oxides with good quality are defined. Preliminary results of the electrical characterization performed on test capacitors are shown.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
