The use of multiple voltage levels introduces new challenges for testing multi- ${V_{\mathrm{ dd}}}$ systems-on-chip (SoCs). Time-division-multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the test-access-mechanism (TAM) in the SoC. Single- $ {V_{\mathrm{ dd}}}$ TAM optimization techniques consider neither the highly constrained test environment of multi- $ {V_{\mathrm{ dd}}}$ SoCs nor the benefits provided by TDM, therefore they are not suitable for multi- $ {V_{\mathrm{ dd}}}$ SoCs. In this paper, we propose the first TAM optimization technique for multi- $ {V_{\mathrm{ dd}}}$ SoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a branch-&-bound approach, it quickly identifies the most effective TAM configurations. Experiments using large benchmark SoCs as well as SoCs from industry highlight the benefits of the proposed technique on multi- $ {V_{\mathrm{ dd}}}$ designs, for both single-site and multisite test applications.