Test bus assignment, sizing, and partitioning for system-on-chip

Abstract

The test access mechanism (TAM) is an important element of test architectures for embedded cores and is responsible for on-chip test pattern transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in system-on-chip integration since it directly impacts testing time and hardware cost. In this paper, an efficient genetic algorithm for designing test access architectures while investigating test bus sizing and concurrently assigning cores to test buses is proposed. Experimental results are presented to demonstrate that the proposed TAM optimization methodology provides efficient test bus designs with minimum testing time while outperforming reported techniques.