Low-Area Wrapper Cell Design for Hierarchical SoC Testing

Abstract

System-on-chip (SoC) integrated circuits are designed and fabricated with multiple levels of hierarchy. However, most previous works on wrapper design, test access mechanism optimization and test scheduling did not take care of the hierarchy properly, thus the corresponding test schedules were often invalid for SoCs with hierarchical cores. We propose a low-area wrapper cell design which can treat SoCs with hierarchy properly and allows simultaneous testing of parent and child cores. The proposed cell uses 13%~23% less area than a recently proposed cell design in equivalent gate count. As a result we achieve up to 21% area reduction for hierarchical ITC '02 SoCs compared to the most recently proposed designs.