Ternary Full Adder Research Articles

Enhanced CPU Design for SDN Controller.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

21T Ternary Full Adder based on Capacitive Threshold Logic and Carbon Nanotube FETs

21T Ternary Full Adder based on Capacitive Threshold Logic and Carbon Nanotube FETs

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

<span>The number of consumers for different applications has expanded tremendously as a result of the growth of consumer electronics-related applications in numerous sectors. Customers often need high-speed applications that use a minimal amount of power for a variety of applications like signal processing, picture processing, communication systems, and so on. The speed of a ternary logic-based design might be greater than that of a binary logic-based one. In this study, a novel architecture for arithmetic and logic units (ALUs) is proposed. The design makes use of ternary logic. In order to accomplish both low power consumption and high performance, methodologies for designing carbon nanotube-based field-effect transistors (CNTFETs) are employed. The method that has been suggested is able to carry out operations such as addition, subtraction, multiplication, reasoning, and comparison. After developing the recommended model, it is compared to earlier designs for power delay product (PDP), average power consumption, and maximum delay duration. The simulation findings show that the carbon nanotube field effect transistors (CNTFET) based ternary ALU circuits outperformed conventional ternary full adder circuits. The suggested design had a delay time of 13.94 ps and a PDP of 5.32 aJ, while the old design had a delay time of 17.67 ps and a PDP of 51.38 aJ.</span>

Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular. Out of numerous ternary logic devices, carbon nanotube (CNT) FET (CNTFET) is considered a good candidate over silicon FETs. Hence, in this study, ternary schematics are developed based on Pseudo N-type CNTFETs. The ternary basic designs such as standard ternary inverter (STI), AND and OR gates are presented. Then, using the proposed basic logic gates, the complex designs such as full adder and full subtractor are also proposed. The HSPICE simulator is utilized to design proposed circuits and analyze different performance parameters. The performance such as delay, power and power delay product (PDP) are analyzed for the proposed circuits. Moreover, the proposed schematics performances are also compared to complementary schematics. It investigated that Pseudo N-type CNTFET schematics improved the overall performance on an average up to 65.82% over the complementary ternary circuits.

Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers.

The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature.

Performance Comparison of CMOS and NMOS GNRFET Full Adder

Transistor makes up the cornerstone of modern computing. In this work, a SPICE model of GNRFET was used to simulate the performance of a NMOS and CMOS binary full adder. The performance of this adder was evaluated in terms of its average power consumption and propagation delay. Three variables, namely the resistance value, dimer lines and channel length were manipulated and the impact on its performance was assessed. It was observed that a linear improvement in propagation delay was accompanied by an exponential increase in power consumption and only a small range of values of resistance was able to deliver a relatively reasonable trade-off between power consumption and propagation delay. These values range from approximately 110 kΩ to 130 kΩ. When the dimer lines were varied from 12 to 8 and channel length was varied from 32 nm to 16 nm, the results showed that a channel length of 16 nm was superior to that of a channel length of 32 nm as it showed 25.25 % of improvement in propagation delay at approximately similar power consumption. On the other hand, the choice of dimer lines and circuit architecture was required to be evaluated on a case-by-case basis. For a compute-intensive application with a controlled environment, NMOS logic with 8 dimer lines should be chosen, while for less compute-intensive applications and portable devices, CMOS logic with 12 dimer lines should be utilised. A NMOS logic was chosen for the former due to a reasonable trade-off of 30.94 % of power consumption for a 35.03 % of propagation delay was established When the performance of these full adders are compared to that of a MTGB based ternary gate in terms of their performance, it was found that the CMOS and NMOS logic full adder performed better than a MTGB based ternary full adder.

Demonstration of Anti-ambipolar Switch and Its Applications for Extremely Low Power Ternary Logic Circuits.

Anti-ambipolar switch (AAS) devices at a narrow bias region are necessary to solve the intrinsic leakage current problem of ternary logic circuits. In this study, an AAS device with a very high peak-to-valley ratio (∼106) and adjustable operating range characteristics was successfully demonstrated using a ZnO and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene heterojunction structure. The entire device integration was completed at a low thermal budget of less than 200 °C, which makes this AAS device compatible with monolithic 3D integration. A 1-trit ternary full adder designed with this AAS device exhibits excellent power–delay product performance (∼122 aJ) with extremely low power (∼0.15 μW, 7 times lower than the reference circuit) and lower device count than those of other ternary device candidates.

Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.2\times - 17.3\times $ </tex-math></inline-formula> , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.

A ternary memristor full adder based on literal operation and module operation

AbstractA ternary memristor full adder is designed based on the literal operation and module‐3 plus operation. Literal operation and module‐3 plus operation are the important operations in the tri‐valued algebra system. Multiple‐valued logic can increase the amount of information carried by the signals and reduce the number of devices and connections. The combination of multiple‐valued logic and memristor is an exploration of new devices and new structures. The novel ternary memristor full adder owns the advantage of simpler structure without decoding units to convert ternary signals to binary at the terminals, and all the signals operated by the circuit are ternary. Compared with the traditional ternary full adder, the number of devices and the power consumption are greatly reduced. Simulation results of different memristor models verified the correctness and applicability of the circuit design. It provides a new idea for the design method of memristor circuits, especially multiple‐valued memristors.

Physical proof and design of ternary full adder circuit in ternary quantum‐dot cellular automata technology

AbstractDownsizing computational modules can be effective in increasing computational speed, reducing energy consumption, and reducing the occupied area of the chip, but limitations associated with Complementary metal–oxide–semiconductor (CMOS) technology downsizing prompted researchers to look for alternative methods for transistors and circuit fabrication. A common issue in many of these methods is the move toward the production of components of logical circuits in nano dimensions. Quantum‐dot cellular automata (QCA) technology is inherently fast and is based on Coulomb interactions, and this property can make the design of computational circuits much easier. The main purpose of this paper is to design a new full adder circuit structure based on ternary quantum‐dot cellular automata technology with physical proofs. Accordingly, the proposed diagram block structure full adder circuit based on ternary QCA (TQCA) is presented, which includes 11 cells, the area is and, the circuit cost is 0.044. For validation, the proposed structure was simulated with TQCAsim software. The results show a significant improvement in circuit parameters.

Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs

In recent decades, the performance of binary computers has escalated through transistor scaling. However, due to the impotent forecasts of transistor scaling, ternary systems are regaining attention. Among many ternary device candidates, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design various terna-ry logic based on memristors and MOSFETs from primitive logic to sequential logic and perform a thorough diagnosis for circuit design. We highlight design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions such as “Strength Design.” Then, we report a proper design methodology of sequential circuits considering the spike phenomena of memristor-based gates. We present 16 novel ternary logic cells and circuitry, including the design of the first balanced ternary full-adder (TFA) and memristor-based ternary pulsed-latch (MTPL). By our TFA, we emphasize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future. Besides, the proposed MTPL uses 16 transistors and 10 memristors, and it occupies only 72.7% of the silicon area, compared to the master-slave ternary flip-flop.

Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs

ABSTRACT This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs.

A low-power dynamic ternary full adder using carbon nanotube field-effect transistors

Ternary logic uses fewer interconnects than binary logic, and smaller voltage swings are required for the same information transfer. Carbon Nanotube transistors (CNFETs) have many advantages over Metal Oxide Semiconductor transistors (MOSFETs), such as equal mobility of electrons and holes, the ability to adjust the threshold voltage by changing the nanotube's diameter, and lower leakage power. In this paper, a dynamic ternary full adder is presented using CNFETs. Subsequently, a 5-trit ripple carry adder is designed based on the proposed dynamic ternary full adder and buffer circuits. The proposed hybrid circuits are designed using clocked dynamic logic. Synopsys HSPICE simulator and Stanford's 32-nanometer CNFET model are used to simulate the circuits. The performance of the approach is evaluated under different supply voltages, loads, and temperatures. It is shown that the proposed full adder has lower power consumption, transistor count, PDP, and EDP compared with previously presented ternary adders. Furthermore, the proposed circuit is more robust to process variations.

Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell

Full adder cell is an important module in arithmetic and processing systems whose performance has a great impact on performance of the whole system. By continuous scaling of the MOS transistors, some challenges and problems appear such as high leakage dissipation for which emerging technologies have been studied as a solution. Carbon nanotube field effect transistor (CNFET) is one of the most potential alternatives for the traditional MOSFET. The threshold voltage of a CNFET can be adjusted by tuning its CNT diameter. This property makes them to be appropriate for designing voltage mode multi-valued logic circuits. In this paper, a novel multiplexer-based ternary full adder cell using CNFET is presented. The proposed circuit is simulated and compared with the state-of-the-art designs using Synopsys HSPICE simulator. Simulations are done to investigate the effect of process (P), voltage (V) and temperature (T) variations on the circuit. The results show that the proposed design reduces the energy consumption by about 54% than the best reported design, while is robust against PVT variations.

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

A novel reversible ternary coded decimal adder/subtractor

Reversible ternary logic is a promising new research for the future of quantum computing, which has several advantages over the binary ones. In this paper, an effective design of reversible ternary coded decimal (TCD) adder/subtractor is proposed. For this purpose, at first, we propose a new reversible ternary full-adder, called comprehensive reversible ternary full-adder, using the ternary logic capabilities that can sum four ternary values and produce two ternary outputs. Moreover, we implement a 3-qutrit ripple carry adder (RCA). Then, we propose a quantum realization of TCD error detector circuit. Next, a novel quantum reversible TCD adder and a novel quantum reversible TCD subtractor are designed and implemented using the proposed 3-qutrit RCA and the proposed TCD error detector. Finally, by merging these two circuits, we propose an effective quantum realization of reversible TCD adder/subtractor. The results of evaluations show that the proposed circuits are superior or similar to related counterpart works in terms of constant input, garbage outputs, hardware complexity and quantum cost criteria.

A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics

Using multi-valued logic can lead to reducing the interconnections in the chip. Reducing the interconnection, in turn, leads to decreasing the chip area and interconnections power dissipation. The design of the multi-valued logic circuits should be performed with the minimum complexity to fulfill the multi-valued logic aim. In the recent years, much research has been focused on the design of multi-valued logics in nanoelectronics due to the high capability of nanoelectronics to design them. In this paper, first, a novel single-supply ternary successor and predecessor are designed based on the multi-threshold voltage in CNFET, which is more energy efficient than those in the previous works. Then, these are used to design the ternary full adder. To reduce the number of transistors in the proposed full adder, the structure of this full adder is designed so that only one successor and predecessor are used and some common portions can be used in the sum and carry generator, and this is shown by equations. The number of transistors in the proposed single-supply full adder is reduced from 132 in the best previous single-supply full adder to 54. Also, to enhance the PDP, the successor and predecessor are used in the quad-state mode (‘0’, ‘1’, ‘2’ and ‘z’: high impedance), where in the ‘z’ mode, the direct current path is cut off. The circuits are simulated by the HSPICE software, using the Stanford 32 nm CNTFET library. The simulation results confirm the correct operation of the proposed circuit and PDP improvement in the proposed ternary full adder, which is about 81.12%, as compared to the best single supply reported in the previous works.

DPL-based novel CMOS 1-Trit Ternary Full-Adder

ABSTRACT This paper presents a new high-speed, low-power, area-efficient 1-trit Ternary-Full-Adder (TFA) as a building block for wave-pipelined ternary-digital system design. Balanced input capacitance with structural symmetry makes Double Pass-transistor Logic (DPL) an ideal candidate for this, and is employed here hence. Design-strategy with working-principle is presented. The TFA is designed and optimised on normal-process-enhancement-type MOS devices that use BSIM4 model-parameters, on 1.0 V supply-rail at 27°C temperature. Simulations are carried out using Tanner EDA V.16. The ternary values ‘0’, ‘1’ and ‘2’ are coded with 0 V, 0.5 V and 1.0 V, respectively. The circuit is time-equalised through coarse and fine-tuning for all data paths from input-to-output to offer efficient wave-pipelining feature. The transient response from T-Spice simulation is validated for all test-patterns. Physical design of proposed TFA is completed using TSMC 65 nm Single-Poly-Double-Metal (SPDM) CMOS process-technology using Microwind3.1. After DRC, LVS and parasitic extraction, the post-layout simulation is done. PVT analysis with statistical PVT (Process-Voltage-Temperature) variation is used to find a worst-case speed-power response of the TFA. Propagation delay is examined for all test patterns and is found satisfactory ensuring effective wave-pipelining. Comparative study with recent candidate designs reveals nearly 21.43% PDP-reduction over the best reported.