Ternary Content Addressable Memory Design Research Articles

Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices.

Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memory (LiM) computing applications. In this paper, we analyze the temperature-dependent device and circuit characteristics of the floating gate field effect transistor (FGFET) source drain barrier (SDB) and FGFET central shallow barrier (CSB) identified in previous papers, and their applicability to LiM applications is specifically confirmed. These FGFETs have the advantage of being much more compatible with existing silicon-based complementary metal oxide semiconductor (CMOS) processes compared to devices using new materials such as ferroelectrics for LiM computing. Utilizing the 32 nm technology node, the leading-edge node where the planar metal oxide semiconductor field effect transistor structure is applied, FGFET devices were analyzed in TCAD, and an environment for analyzing circuits in HSPICE was established. To seamlessly connect FGFET-based devices and circuit analyses, compact models of FGFET-SDB and -CSBs were developed and applied to the design of ternary content-addressable memory (TCAM) and full adder (FA) circuits for LiM. In addition, depression and potential for application of FGFET devices to neural networks were analyzed. The temperature-dependent characteristics of the TCAM and FA circuits with FGFETs were analyzed as an indicator of energy and delay time, and the appropriate number of CSBs should be applied.

A Novel Cascadable TCAM Using RRAM and Current Race Scheme for High-Speed Energy-Efficient Applications

In this work, a novel ternary content addressable memory (TCAM) design is proposed using resistive random-access memory (RRAM) array in 2T2R configuration. The suggested memory array adopts the current-race (CR) sensing mechanism incorporated with a match-line (ML) booster in the sensing amplifier (SA) to improve energy efficiency, search speed and tolerance to RRAM switching variation. Several innovations are implemented to enhance the design further. For large TCAM arrays, match-line sensing amplifier (MLSA) direct cascading (DC) and an SR-latch cascading (SRC) schemes are proposed and compared in search speed, energy efficiency and MLSA noise margin. A same clock phase cascading (SCPC) scheme is also introduced to reduce latency in cascading structure by placing evaluation phase of all stages in the same clock phase. Furthermore, an RRAM-based tunable delay element (RRAM-TDE) is used in the TCAM design to provide flexibility and robustness against RRAM switching variation. The resulting system demonstrates excellent speed, energy and area efficiency against other TCAM designs using CMOS and emerging non-volatile memory (eNVM). To the best of our knowledge, the proposed 64-bit 1-stage TCAM system's speed and energy consumption match the best performance reported by other eNVM-based TCAM designs. The proposed design on a 128-bit 2-stage system also has speed and energy consumption comparable to SRAM-based TCAMs with the extra advantages of (a) compact size (90% reduction) and (b) non-volatility.

Memtransistor-Based Ternary Content-Addressable Memories: Design and Evaluation

The memtransistor (MT) based on 2-D materials is considered a promising candidate to extend Moore’s law, thanks to its scalability. As a hybrid integration of a memristor and a transistor, MT combines the electrical properties of memristor-based one-transistor one-resistor (1T-1R) structures (i.e., nonvolatile resistive switching and gate selection) into a single compact device. In this work, we evaluate MT technology from an application perspective and explore its use in ternary content-addressable memory (TCAM) systems. Based on characterization data from a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${10} \times {10}$ </tex-math></inline-formula> MoS2-based MT crossbar array, we propose two designs of MT-based TCAM (i.e., bitcells and TCAM array implementations and layouts). We also explore the design space of TCAM parameters and compare the performance and reliability of the proposed TCAM designs. In particular, we demonstrate that the use of MT technology facilitates the implementation of long TCAM words (>2 kbits) at low MT resistance ratios and search voltages, which is desirable for long TCAM endurance.

A Highly Compact Nonvolatile Ternary Content Addressable Memory (TCAM) With Ultralow Power and 200-ps Search Operation

In this work, we developed a nonvolatile ternary content addressable memory (TCAM) with a cell size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.01~\mu \text{m}^{{2}}$ </tex-math></inline-formula> utilizing the Ge-based memory diode (MD), which has the most area-efficient TCAM design reported. The MDs have a high current ratio between ON and OFF states and a large rectifying ratio, showing the potential usage in large-dimension TCAM arrays. Besides, the functionality of parallel search was demonstrated with a 2-bit MD-TCAM array by experiment, and the electrical characterization showed expected results. With the help of the sub-ns ultrafast measurement system, it is confirmed that the search energy of MD-TCAM could reach as low as 1.0 fJ/bit/mismatch, and one search operation can be performed within 200 ps. Furthermore, the circuit-level simulation results verified that the MD-TCAM developed in this study shows good performance in 128-bit parallel searching, which is promising for the ultrafast and low-power data search applications in the coming IoT era.

Algorithmic TCAM on FPGA with data collision approach

&lt;span&gt;Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.&lt;/span&gt;

Efficient TCAM design based on dual port SRAM on FPGA

&lt;span&gt;&lt;span&gt;Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update speed at 75 million rules per second. The architecture is configurable, allowing various performance trade-offs to be exploited for different ruleset characteristics&lt;/span&gt;.&lt;/span&gt;

Design and Analysis of Power‐Efficient Quasi‐Adiabatic Ternary Content Addressable Memory (QATCAM)

Ternary content addressable memory (TCAM) is a high-speed memory employed in network search engines which consume significant power. Many authors have provided efficient power solutions by proposing different match line schemes. This study proposes the use of energy recovering adiabatic logic scheme in the design of power-efficient TCAM. Two different innovative quasi-adiabatic TCAM (QATCAM) core cells are designed. The design is implemented in 180 nm complementary metal-oxide semiconductor technology with a power clock of 1.8 V on Cadence Virtuoso. It is found that the power dissipated by the proposed QATCAM cells is lower than its conventional counterparts. Adiabatic TCAM arrays are designed using adiabatic peripheral circuits. The proposed adiabatic TCAM core cells yield more considerable power savings even at higher frequencies up to 1 GHz.

Data Retention-Based Low Leakage Power TCAM for Network Packet Routing

The ternary content addressable memory (TCAM) is widely used in the routing table due to its high lookup performance. However, a large number of transistors would cause the power consumption of TCAM to be considerable. In this brief, a new state-preserved technique, named data retention based TCAM (DR-TCAM), is proposed to reduce the leakage power dissipated in the TCAM memory. According to the continuous feature of mask data, the DR-TCAM can dynamically adapt the power source of mask cells so as to reduce the TCAM leakage power. Particularly, the mask data wouldn’t be destroyed in the DR-TCAM. Based on TSMC 40nm technology, the simulation results show that the DR-TCAM performs better than the state-of-the-art works. Compared to the traditional TCAM design, the DR-TCAM can deliver a TCAM leakage power reduction of 41% for a collection of real routing tables. Besides, the total power reduction is about 12%.

Ternary Content Addressable Memory

Memory Technology plays a vital role in fast searching applications. Content Addressable Memory (CAM) is a special type of memory used for search operation. CAM provides access to the stored data by its content instead of the address. Advanced version of CAM is known as Ternary CAM (TCAM) which is a memory that can also store don’t care bit. TCAM is most relevant in routers in networking applications. Review of TCAM design techniques at different aspects are carried out, and obtained that an Energy Efficient TCAM (EE-TCAM) is the one which is having less power consumption. Compared with other SRAM-based TCAM designs, EE-TCAM use up reduced energy as it selectively activates only one row of SRAM at a time for search operation instead of activating the whole SRAM memory as in the other architectures. Partitioning of the TCAM table, designing of a pre-classifier and memory mapping are done prior to the work. This paper focuses on designing an EE-TCAM using Verilog HDL on Zybo7000 platform using Vivado design suite. Functional analysis of a 6*6 EE-TCAM is performed and power, delay and resource utilization are obtained. From the obtained results it is clear that EE-TCAM is having very less power and delay.

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

Static random access memory (SRAM)-based ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) is used for packet classification in software-defined networking (SDN) and OpenFlow applications. SRAMs implementing TCAM contents constitute the major part of a TCAM design on FPGAs, which are vulnerable to soft errors. The protection of SRAM-based TCAMs against soft errors is challenging without compromising critical path delay and maintaining a high search performance. This brief presents a lowcost and low-response-time technique for the protection of SRAM-based TCAMs. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. This technique exploits the binary-encoded TCAM table maintained in SRAM-based TCAMs for update purposes to implement a low-response-time error-correction mechanism at low cost. The error-correction process is carried out in the background, allowing lookup operations to be performed simultaneously, thus maintaining a high search performance. The proposed technique provides protection against soft errors with a response time of 293 ns, whereas maintaining a search rate of 222 million searches per second on a 1024 × 40 size TCAM on Artix-7 FPGA.

A Power Efficient Improved NOR-Type TCAM Design using OR-Type Match-Line Segment

This paper presents the novel way to deal with diminish power utilization in a ternary content addressable memory (TCAM) designed in current innovation. The main aim of this TCAM design is to reduce the dynamic power consumption. In TCAM large amount of the power consumption happens during search operation, so we focussed on this area. Here right now give pragmatic plan of a TCAM which is arranged for low-power applications. Simulation of this design has done in Tanned EDA V.16 tool. For simulations of Low power TCAM designs we used predictive technology model (PTM) 45nm for high-performance applications which include metal gate, high-k and stress impact of CMOS technology.

RETRACTED: Reconfigurable parallelized TCAM architecture based on enhanced static memory cell

Abstract Associative memories with tristate-based web crawlers assume a vital job in systems administration switches. The hunt space requests of ternary associative memories applications are always rising. In any case, existing acknowledge where content addressable memories can enter door clusters gate arrays experience the ill effects of capacity wastefulness. The proposed idea introduces high speed search engines empowered and intertwined with many internal ports of static memory cell put together ternary associative memories structure comparing with FPGA, to accomplish an effective usage of static arrangement of memories. Previous versions of static memory cell's exploits answers for this renewable solution and also diminish maximizing expansion provided in this customary Ternary content addressable memory design specifications leading with rapid and enormous development of static memories on behalf of unique utilizing fell square Static memories called block random access memories (BRAMs) over the boards of FPGA. Nonetheless, best in class FPGAs which entitled as block RAM have a base profundity restriction, which confines the capacity productivity for ternary associative memories bits. Our proposed arrangement maintains a strategic distance from this restriction with a provision of uniting and linking the customary idea of ternary memories and its table split-ups as an alternative of partitioned squares which is so called arranged block RAMs, along these lines accomplishing associative and productive ternary CAM memory structure. The arrangement works as arrangement of basic double block memories which was planned as static memories of many input and output ports which utilizing higher parallelism, influencing speeder and vital inner clock recurrence for getting partial-squares leading to block random memories in unique individual framework cycle. Actualized this novel structure on a Virtuoso environment of version six field programmable gate array gadget. Contrasted and in the earlier versions of gate array ternary content memories plans, this strategy accomplishes speeding of two and half of its occasions faster execution of its memory unit cycle.

Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment

Ternary content-addressable memory (TCAM) is a popular component to use for fast and parallel data searching. However, with technology downscaling, TCAM consumes huge leakage power, which affects search performance. To control TCAM's leakage power consumption, this paper proposes a multiple-segment voltage self-controlled TCAM (VoSCT) that varies the back-gate voltages of fin field-effect transistors and the supply voltages of a TCAM entry. In the VoSCT, a TCAM entry is partitioned into several segments, and each segment operates in one of the three following modes: high-speed mode, low-power mode, and ultra-low-power mode. Examples that use a real routing table are employed to verify the feasibility of the proposed VoSCT, and the experimental results indicate that 38% of leakage power and 21% of total power can be reduced with only a 9% search delay increase and 4% area overhead increase compared with the traditional TCAM design.

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

Ternary content-addressable memory (TCAM) designed using static random-access memory (SRAM)-based field-programmable gate arrays (FPGAs) offers a promising lookup performance. However, the update process in a TCAM table poses significant challenges for efficiently employing SRAM-based TCAM. SRAM-based TCAM for FPGAs is designed using block RAM or distributed RAM resources in FPGAs. Such designs suspend search operations during an already high-latency update operation, rendering them infeasible in applications that require high-frequency updates. This paper presents a dynamically updatable energy- and resource-efficient TCAM design (DURE) based on FPGAs. DURE exploits the distributed RAM resources in FPGAs. More specifically, the lookup table RAMs (LUTRAMs) available in SLICEM resources are configured as quad-port RAM, which constitutes the basic memory (BM) block in the implementation of DURE. The contents of the TCAM table are divided into chunks of equal size and mapped onto the LUTRAMs of the proposed BM blocks. DURE implements dynamic updates by reconfiguring the LUTRAMs of only those BM blocks that are associated with the word being updated, thereby allowing search and update operations to be performed simultaneously. This achieves a lookup rate of 335 million lookups per second, with an update rate of 5.15 million updates per second on a 512 × 36 size TCAM on a Virtex-6 FPGA. Compared with the existing SRAM-based TCAMs, DURE has a smaller single-cycle search latency and achieves at least 2.5 times more energy efficiency and a 67% higher performance per area.

Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits

Among the beyond-complementary metal–oxide–semiconductor (CMOS) devices being explored, ferroelectric field-effect transistors (FeFETs) are considered as one of the most promising. FeFETs are being studied by all major semiconductor manufacturers, and experimentally, FeFETs are making rapid progress. FeFETs also stand out with the unique hysteretic $I_{\text {ds}}$ - $V_{\text {gs}}$ characteristic that allows a device to function as both a switch and a nonvolatile (NV) storage element. We exploit this FeFET property to build two categories of fine-grained logic-in-memory (LiM) circuits: 1) ternary content addressable memory (TCAM) which integrates efficient and compact logic/processing elements into various levels of memory hierarchy; 2) basic logic function units for constructing larger and more complex LiM circuits. Two writing schemes (with and without negative supply voltages respectively) for FeFETs are introduced in our LiM designs. The resulting designs are compared with existing LiM approaches based on CMOS, magnetic tunnel junctions (MTJs), resistive random access memories (ReRAMs), ferrorelectric tunnel junctions (FTJs), etc., that afford the same circuit-level functionality. Simulation results show that FeFET-based NV TCAMs offer lower area overhead than MTJ (79%) and CMOS (42% less) equivalents, as well as better search energy-delay products (EDPs) than TCAM designs based on MTJ ( $149\times $ ), ReRAM ( $1.7\times $ ), and CMOS ( $1.3\times $ ) in array evaluations. NV FeFET-based LiM basic circuit blocks are also more efficient than functional equivalents based on MTJs in terms of propagation delay ( $4.2\times $ ) and dynamic power ( $2.5\times $ ). A case study for an FeFET-based LiM accumulator further demonstrates that by employing FeFET as both a switch and an NV storage element, the FeFET-based accumulator can save area (36%) and power consumption (40%) when compared with a conventional CMOS accumulator with the same structure.

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512 x 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

Low Power Spintronic Ternary Content Addressable Memory

Ternary Content Addressable Memory (TCAM) is used in applications that require a low power dissipation and fast data retrieval. This paper presents a domain wall-based spintronic TCAM cell. The proposed design exploits the resistive behavior of this nonvolatile memory, reduces total power dissipation by reducing the voltage swing at the match line, and minimizes delay by employing a tiny sensing unit within each cell. Our experimental evaluation on 45 nm technology for a 256-bit word-size TCAM at an 1 V supply voltage and 50 mV sense margin show that the delay is less than 200 ps. The per-bit search energy is approximately 3 fJ. Experimental evaluation on benchmark applications on the AMD Southern Islands GPU reveal that the GPU always dissipates less power when enhanced with the proposed TCAM design. Furthermore, the proposed method consumes at least 30% less energy when compared to state-of-the-art TCAM designs.

A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy

A novel ternary content addressable memory (TCAM) design based on resistive random access memory (RRAM) is presented. Each TCAM cell consists of two parallel RRAM to both store and search for ternary data. The cell size of the proposed design is 8F2, enable a ∼60× cell area reduction compared with the conventional static random access memory (SRAM) based implementation. Simulation results also show that the search delay and energy consumption of the proposed design at the 64-bit word search are 2 ps and 0.18 fJ/bit/search respectively at 22 nm technology node, where significant improvements are achieved compared to previous works. The desired characteristics of RRAM for implementation of the high performance TCAM search chip are also discussed.

NV-TCAM: Alternative designs with NVM devices

TCAM (ternary content addressable memory) is a special memory type that can compare input search data with stored data, and return location (sometime, the associated content) of matched data. TCAM is widely used in microprocessor designs as well as communication chip, e.g., IP-routing. Following technology advances of emerging nonvolatile memories (eNVM), applying eNVM to TCAM designs becomes attractive to achieve high density and low standby power. In this paper, we examined the applications of three promising eNVM technologies, i.e., magnetic tunneling junction (MTJ), memristor, and ferroelectric memory field effect transistor (FeFET), in the design of nonvolatile TCAM cells. All these technologies can achieve close-to-zero standby power though each of them has very different pros and cons.

CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection

The rapid growth in network bandwidth and the ever more sophisticated network attack techniques pose challenges to current network intrusion detection systems (NIDS). While software-based solutions are incapable of performing wire-speed network traffic monitoring, many hardware-based pattern matching solutions also suffer from capacity limitation and high power consumption. To effectively address these challenges, we propose a reconfigurable complex matching accelerator (CMA) enabled by the emerging nonvolatile memory technology (resistive random access memory) to speed up intrusion detection systems with better energy efficiency. Beyond common equality matching in current NIDS, CMA can be configured to provide a comprehensive set of arithmetic matching functions (e.g., less than), resulting in improved utilization and higher energy efficiency. We evaluate CMA using real-world network security benchmarks. On average, it achieves 84.9 percent area reduction, 97.3 percent energy consumption reduction, and 20 percent improvement in searching speed compared to the SRAM-based Ternary Content Addressable Memory (TCAM) design in state-of-the-art NIDS. It also outperforms emerging RRAM-based TCAM (2.5T1R) design in area, energy and search delay, on the set of evaluated workloads.