Terms Of Power Delay Product Research Articles

A glitch free variability resistant high speed and low power sense amplifier based flip flop for digital sequential circuits

In this work, a sense amplifier based flip flop (SAFF) is presented appropriate for high speed, high data activity and low power operations. The delay and power of the proposed flip flop have been considerably reduced as it uses a novel single-ended latch structure. The flip flop (FF) also achieves glitch free operation and can be operated and is functional at near-threshold voltage levels. SPICE simulations were carried out to do a comprehensive and quantifiable analysis between the presented architecture and formerly known architectures in 32 nm CMOS technology. The proposed design achieved a reduction of minimum 22.67% in power at nominal voltage. In terms of Power Delay Product (PDP), a reduction of 63.51% was observed. At 100 MHz clock frequency, the power dissipation was lowered by 30%. The proposed design at data activity of 100% consumes 28.24% less power whereas at activities of less than 12.5% it does not show significant improvements. However, the proposed design has an advantage in terms of speed and is 40% to 82% faster at nominal conditions and can also operate at wide supply voltage. It also has the second lowest transistor count and second lowest area. The power performance is verified by implementing the proposed design as a 4-bit shift register.

SAMA: Self-adjusting multi-cycle approximate adder

Approximate computing is a promising approach that leads to a better compromise between power and delay by trading an acceptable level of accuracy in inherently error resilient applications. In this paper, we present a runtime accuracy configurable approximate adder that can operate in both approximate and exact modes. It provides a better compromise between power, delay, and accuracy compared with state-of-the-art approximate adders at high accuracies. Our evaluations show that the proposed adder can make up to 45% and 79% improvements in power-delay product (PDP) and energy-delay product (EDP), respectively, compared with state-of-the-art approximate adders, at high accuracies. In the accurate mode, the improvements in the PDP and EDP are up to 58% and 82%, respectively. The use of the proposed adder in an image processing application and in a mean-squares prediction algorithm confirms its superiority over existing circuits in terms of PDP and EDP.

Delay analysis of mixed CNT bundles as global interconnect for nanotechnology nodes

Abstract This paper presents modeling of high current capability of mixed carbon nanotube (CNT) bundle interconnects depending upon the type of constituent CNT materials and their orientations. With different arrangements, one category of novel mixed CNT bundles formed by the combination of multi-walled/multi-shell CNT and double-shell CNT bundles (MDCB) are proposed and compared with the mixed CNT bundles (MSCB) formed with multi-shell CNT and single-walled CNT bundles. A time-domain analysis is performed for these structures to analyse the effect of delay and power dissipation. It has also been observed that MDCB structures give better performance (≈ 30%) than MSCB structures in terms of power-delay product at the global length of interconnect for nano-regime technology nodes. Also, MDCB structure formed by placing multi-walled CNTs along the periphery and double-walled CNTs in the centre of structure yields the best result against all proposed mixed CNT bundled structures and can be employed for future interconnect applications.

High-Speed and Energy-Efficient Carry Look-Ahead Adder

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation

Approximate computing (AC) has been considered as a promising paradigm to improve the energy-efficiency of computing hardware for error-tolerant applications, with negligible quality degradation to the output. Dividers frequently limit the performance of a computing system; however, they have not received as much attention as multipliers and adders in AC. In this paper, an energy-efficient and high-performance approximate divider is proposed based on logarithmic conversion and piecewise constant approximation. In this design, the range for the conversion between binary and logarithmic numbers is first expanded from <inline-formula> <tex-math notation="LaTeX">$\mathbf {[{0,1}]}$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$\mathbf {[-0.5,1]}$ </tex-math></inline-formula>. A heuristic search algorithm is then devised to find the most accurate constant set to approximate the reciprocal of the divisor, by minimizing a statistical error. The hardware implementation is presented for both floating-point (FP) and integer dividers. With a high configurability, the proposed divider results in a mean relative error distance (MRED) from 2.78&#x0025; to 0.046&#x0025;, indicating a high accuracy among state-of-the-art approximate dividers. Compared to the half-precision FP divider, the proposed divider with a MRED of 0.74&#x0025; can achieve nearly <inline-formula> <tex-math notation="LaTeX">$\mathbf {90\times }$ </tex-math></inline-formula> improvement in PDP. Moreover, compared to state-of-the-art approximate dividers, the proposed design is in the Pareto Frontier in terms of power delay product (PDP) and MRED. The three image processing application results demonstrate that the proposed divider can result in the highest peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) even with truncation.

Hybrid Dynamic CML with Modified Current Source (H-MDyCML): A Low-Power Dynamic MCML Style

With the growing demands of portable devices, it is necessary to pay attention to low-power digital integrated designs. This paper proposes a low-power MOS Current Mode Logic (MCML) design, termed as Hybrid Dynamic Current Mode Logic with modified current source (H-MDyCML). In H-MDyCML circuits, the functions are realized using complementary pass transistor logic which helps to overcome the problem of stacking of transistors in multiple levels. The dynamic current source has also been modified from an NMOS transistor to a PMOS transistor-driven current source which leads to the elimination of the use of CMOS inverter. H-MDyCML circuits are compared with other existing designing styles: Dynamic CML (DyCML), Hybrid DyCML (H-DyCML), and DyCML with modified current source (Dy-CML-NP). The proposed design (H-MDyCML) shows an overall improvement (in terms of Power Delay Product (PDP)) up to 94.77% compared to DyCML, 52.17% compared to Dy-CML-NP, and 91.40% compared to H-DyCML, for single stage circuits.

Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

With the advancement in technology, various designs of multipliers offering low power consumption, high speed and less area have been proposed by many researchers. The main concern of electronic system designers is the energy minimization with the minimum penalty in speed and area for designing portable devices. Recent development focuses on the design of low-power multiplier for applications like biomedical signal processing requiring the least power consumption and delay-tolerant multiplier. This paper proposes a power-efficient design of the Wallace tree multiplier using a power-efficient 7:3 counter consisting of multiplexer and ex-or gates. The maximum power of the multiplier is consumed in the partial product tree reduction, and hence, in the proposed counter-based modular Wallace tree (CBMW) multiplier partial products are reduced using sequential 7:3 counter and the multi-bit addition in a single column reduces the complexity of the multiplier due to improvement in the locality. These proposed changes make design low power and scalable. The hardware utilization is minimum when a single 7:3 counter is used in partial product tree reduction per stage. The proposed multiplier is implemented in the Xilinx ISE design suite 14.7 using Verilog language on Spartan 3E FPGA. The design is also synthesized in Synopsys Design Compiler using 180 nm CMOS technology cell library. The corner analysis of the proposed design is performed in Synopsys PrimeTime, and the design meets all timing specifications. Also, the multiply and accumulate (MAC) unit is designed using the proposed multiplier to demonstrate an application of it. The detailed comparison is performed for 8-bit as well as 16-bit operands, and it shows that the CBMW multiplier gives better delay performance and consumes the least power compared to existing multipliers. It is proved to be an efficient multiplier in terms of Power-Delay Product (PDP). The power consumption of the proposed 16 $$\times $$ 16 multiplier is 88.16 mW and 87.7 $$\mu $$ W for Spartan 3E FPGA and ASIC design for 180 nm technology, respectively. It provides a promising performance for FPGA as well as for the ASIC platform.

Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology

In this brief, different characteristics of current starved ring oscillator (CSRO) circuits are investigated and four new designs are proposed. A new parameter, known as phase noise bandwidth product (PNBP), is also proposed to address the trade-off between phase noise performance and frequency tuning range while designing ring oscillators (ROs). The proposed circuits are compared with existing architectures in terms of power consumption, frequency bandwidth, maximum frequency, phase noise, power delay product (PDP) and PNBP. For performance evaluation, three-stage CSROs have been implemented in Cadence software using the 16 nm PTM High Performance (HP) technology model. Simulation results demonstrate that two newly proposed CSRO architectures using one NMOS sink or one PMOS source have similar optimum results in terms of PDP and PNBP as the existing CSRO using an output switch scheme, but with an advantage of lower area requirement. Moreover, all four proposed architectures show improved performance in terms of PDP and PNBP compared to conventional CSRO. The performance of the CSROs is also observed and compared with respect to the variations in process-voltage-temperature (PVT) parameters.

High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of xor–xnor circuit. In this article, a high-speed, low-power 10-T xor–xnor circuit is proposed, which provides full swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. The proposed circuit reduces the power delay product (PDP) at least by 7.5% than that of the available xor–xnor modules. Four different designs of FAs are also proposed in this article utilizing the proposed xor–xnor circuit and available sum and carry modules. The proposed FAs provide 2%–28.13% improvement in terms of PDP than that of other architectures. To measure the driving capabilities, the proposed FAs are embedded in 2-, 4-, and 8-bit cascaded full adder (CFA) structures. Results show that two of the proposed FAs provide the best performance for a higher number of bits among all the FAs.

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip–flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells

In the past ten years tunnel field effect transistors (TFET) are widely used for its low power performance. To avoid the Boltzmann-limited sub-threshold swing TFET uses the inter-band tunneling as the conduction mechanism. The TFET structure is same as the MOSFET and the switching mechanism differ from it. But, the device parameters process, voltage, and temperature (PVT) variation affects the low power behavior. In this paper we propose a TFET technology to overcome the PVT variations. A new physics model for TFET is first proposed to improve the design parameters to sub-threshold swing, trans-conductance, output conductance, gate threshold voltage, and drain threshold voltage of the proposed device. To improve the PVT awareness based on Boolean logic analysis for the input signals of the extra inserted transistors between the pull-up and pull-down network a PVT independent (INDEP) technique is introduced. INDEP approach not only reduces the leakage current but also mitigates the variability issues with minimum susceptible delay paths. The 6 T SRAM cell is implemented by combining the INDEP model and the proposed physics model. By using HSPICE tool the PVT variations are examined with different TFET technologies. The simulation result shows that the proposed design performs efficient than existing design in terms of power delay product (PDP).

Area and Energy-Efficient 4-2 Compressor Design for Tree Multiplier Implementation

Redundant gates of 4-2 compressor (hereafter, it is referred as 42C) has been removed by simplification of compressor output Boolean expression, that results in power consumption minimization. Further, the proposed design is implemented in full swing gate diffusion input logic, a low-power design technique with minimum transistor count. To evaluate the performance of existing and proposed compressor designs, they are simulated using SPICE simulation at 45 nm technology model. Also, the area is calculated from their corresponding generated layouts for the same technology model. From the simulation results, it is observed that the proposed compressor has shown performance improvement in terms of power delay product by 45% than the recently reported compressor. Further, to study the performance of proposed compressor in an application environment, a 16-bit multiplier is implemented. Its simulation results confirmed that the performance improvement is consistent in the multiplier too.

Wide‐input dynamic range 1 MHz clock ultra‐low supply flip‐flop

A new wide-input dynamic range flip-flop capable of operation at an ultra-low supply voltage of 0.16 V is presented. The proposed flip-flop named as capacitively boosted sense-amplifier flip-flop (CB-SAFF) utilises a capacitively boosted sense-amplifier master stage to sense the data signals and amplify them to a voltage higher than the supply and below the ground for driving the slave latch stage with improved strength. Using the same size of input/output transistors and load capacitance, the proposed CB-SAFF outperforms existing state-of-the-art sense-amplifier flip-flop designs at a low supply voltage operation from 0.16 to 0.6 V in terms of power delay product and clock to output propagation delay performance metrics. In addition, the proposed CB-SAFF can also sample low-swing data signals down to 0.2 V even at a 0.16 V supply voltage and 1 MHz clock frequency, thus making it highly suitable for applications that demand high speed and low power consumption such as for use in ultra-low voltage Internet of Things, wireless sensor nodes and smart motes.

High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

Abstract This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.

Design and Comparative Evaluation of a PCM-Based CAM (Content Addressable Memory) Cell

This paper presents the design of a content addressable memory (CAM) cell. This cell utilizes a phase change memory (PCM) as a storage element and an ambipolar transistor for data comparison; the operation of the ambipolar transistor is controlled by voltage at the polarity gate. A memory core consisting of a CMOS transistor and a PCM is employed (1T1P). For the search operation, the data in the 1T1P memory core are read and its values are established by using a differential sense amplifier. The proposed CAM cell is simulated and compared with other nonvolatile CAM cells by using emerging technologies (such as MTJ and memristor). The simulation results show that as the proposed CAM cell operates on a voltage basis, it offers significant advantages in terms of power delay product for the search operation and reduced circuit complexity (in terms of lower transistor and storage element counts) compared with other designs found in the technical literature.

Power Efficient MAC Unit Based Digital PID Controllers

Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product.

A high-performance low-voltage current-mode min/max circuit

Purpose – Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator. Design/methodology/approach – The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module. Findings – The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature. Originality/value – A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

A Reconfigurable Lighting Engine for Mobile GPU Shaders

A reconfigurable lighting engine for widely used lighting models is proposed for low-power GPU shaders. Conventionally, lighting operations that involve many complex arithmetic operations were calculated by the shader programs on the GPU, which led to a significant energy overhead. In this letter, we propose a lighting engine to improve the energy-efficiency by supporting the widely used advanced lighting models in hardware. It supports the Blinn-Phong, Oren-Nayar, and Cook-Torrance models, by exploiting the logarithmic arithmetic and optimizing the trigonometric function evaluations for the energy-efficiency. Experimental results demonstrate 12.7%, 42.5%, and 35.5% reductions in terms of power-delay product from the shader program implementations for each lighting model. Moreover, our work shows 10.1% higher energy-efficiency for the Blinn-Phong model compared to the prior art.

Performance and analysis of temperature dependent multi-walled carbon nanotubes as global interconnects at different technology nodes

A temperature dependent performance in terms of power delay product (PDP) of multi-walled carbon nanotube (MWCNT) bundle interconnect has been analyzed for temperature range from 200 to 450 K at three different technology nodes viz. 32, 22 and 16nm. A similar analysis is performed for copper interconnect and results are compared with MWCNT bundle interconnect. Comparative results revealed that delay and PDP is increased with rise in temperature ranging from 200 to 450 K. It has also been observed that the temperature dependent MWCNT bundle interconnect gives better performance in terms of delay, power and PDP as compared to copper interconnect for three technology nodes at global interconnect length.

Energy‐efficient static sparse‐tree adder based on MUX‐less bypassing architecture

An energy-efficient 64 bit static sparse-tree adder using a multiplexer (MUX)-less bypassing scheme is proposed for mobile central processing units. Conventionally, bypassing schemes have been used to eliminate unnecessary switching of circuits but have incorporated a large delay overhead due to their output MUX, which reduces the energy efficiency of circuits in terms of power-delay product (PDP). A novel static sparse-tree adder is presented based on a proposed MUX-less bypassing scheme to reduce the delay associated with the conventional bypassing scheme, thereby improving the energy efficiency, i.e. the PDP. Simulation results show a 30% reduction in PDP compared to the conventional bypassing adder and a 13% reduction from the state-of-the-art technique.