Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells

Abstract

In the past ten years tunnel field effect transistors (TFET) are widely used for its low power performance. To avoid the Boltzmann-limited sub-threshold swing TFET uses the inter-band tunneling as the conduction mechanism. The TFET structure is same as the MOSFET and the switching mechanism differ from it. But, the device parameters process, voltage, and temperature (PVT) variation affects the low power behavior. In this paper we propose a TFET technology to overcome the PVT variations. A new physics model for TFET is first proposed to improve the design parameters to sub-threshold swing, trans-conductance, output conductance, gate threshold voltage, and drain threshold voltage of the proposed device. To improve the PVT awareness based on Boolean logic analysis for the input signals of the extra inserted transistors between the pull-up and pull-down network a PVT independent (INDEP) technique is introduced. INDEP approach not only reduces the leakage current but also mitigates the variability issues with minimum susceptible delay paths. The 6 T SRAM cell is implemented by combining the INDEP model and the proposed physics model. By using HSPICE tool the PVT variations are examined with different TFET technologies. The simulation result shows that the proposed design performs efficient than existing design in terms of power delay product (PDP).