A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability

Abstract

This paper presents a FinFET based 6T SRAM cell, with separate read access path and write path, designed by combining the advantages of conventional single ended 5T and the conventional 8T SRAM cells. The proposed SRAM cell achieves 70% and 55% of write performance improvement in terms of Power delay product (PDP) than 8T (also conventional 6T) and 5T SRAM cells respectively. Proposed cell achieves 78% of hold 1 and 40% of hold 0 static power reduction than the conventional 5T, 6T and 8T cells. The proposed cell is read SNM free and also achieves better hold SNM and write ability than 5T and 8T SRAM cells.