Terms Of Hardware Cost Research Articles

Embedding incomplete binary trees into incomplete hypercubes

It has been proved that an incomplete binary tree cannot be embedded into an incomplete hypercube with dilation 1 and expansion 1. By applying some properties of inorder traversal, the authors present an embedding scheme with dilation 2, edge-congestion 2 and expansion ratio (N + 1)/N, where N is the number of nodes in an incomplete binary tree. The authors prove that this embedding is optimal under the constraint of expansion ratio (N + 1)/N. With this embedding scheme, a method is developed that can be used to simulate a binary tree on an incomplete hypercube effectively. Under the distributed environment, the mapping addresses of neighbouring nodes in an incomplete binary tree can be identified in constant time without repeating the mapping work. Furthermore, experimental results show that this scheme is much better than the corresponding best known dilation 1 embedding scheme in terms of hardware costs and implementation. Even in total time costs (addressing time, computation time and transmission time), this approach is quite competitive.

Associative nets: a graph-based parallel computing model

This paper presents a new parallel computing model called Associative Nets. This model relies on basic primitives called associations that consist of applying an associative operator over connected components of a subgraph of the physical interprocessor connection graph. Associations can be very efficiently implemented (in terms of hardware cost or processing time) thanks to asynchronous computation. This model is quite effective for image analysis and several other fields; as an example, graph processing algorithms are presented. While relying on a much simpler architecture, these algorithms have, in general, a complexity equivalent to the one obtained by more expensive computing models, like the PRAM model.

Digital fuzzy logic controller: design and implementation

In this paper, various aspects of digital fuzzy logic controller (FLC) design and implementation are discussed, Classic and improved models of the single-input single-output (SISO), multiple-input single-output (MISC), and multiple-input multiple-output (MIMO) FLCs are analyzed in terms of hardware cost and performance. A set of universal parameters to characterize any hardware realization of digital FLCs is defined. The comparative study of classic and alternative MIMO FLCs is presented as a generalization of other controller configurations. A processing element for the parallel FLC architecture realizing improved inferencing of MIMO system is designed, characterized, and tested. Finally, as a case feasibility study, a direct data stream architecture for complete digital fuzzy controller is shown as an improved solution for high-speed, cost-effective, real-time control applications.

Efficient VLSI array processing structures for adaptive quadratic digital filters

In this paper we introduce a class of efficient architectures for adaptive quadratic digital filters. These architectures are based on the LMS algorithm and use the rank compressed lower-upper (LU) triangular deomposition method. These architectures exhibit high parallelism as well as great modularity and regularity. We also consider affiliated VLSI array processing structures and compare these in terms of hardware cost and data throughput delay. For comparison purposes, the distributed arithmetic structures of adaptive quadratic filters are also included in the paper. Finally, the convergence performance of the adaptive quadratic filters is tested via benchmark simulation examples.

Modular architectures for two-dimensional digital signal processing

The implementation of highly modular two-dimensional (2-D) digital filters is addressed. The idea of matrix decomposition is used to provide increased parallelism and regularity. Four different structures, namely, the transversal, the distributed arithmetic, the stored product, and the systolic array, are considered. For comparison purposes, the direct implementation is included. An analysis of each of each is performed and comparisons are made in terms of hardware cost, cycle time, finite register length effects, and regularity. It is found that the systolic array structure seems to offer the best compromise among the various conflicting figures of merit. The distributed arithmetic structure is shown to be superior in the case of low-order filters, while the stored product structure is preferable for high-order filters. The inherent parallelism and high throughput rate of these structures make them suitable for real-time image processing applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Word reduction in microprogrammed controllers by state-dependent preprocessing of the inputs

Drastic reductions of the number of words in microprogrammed controllers, and proportional savings in terms of hardware cost, can be achieved by a state-dependent mapping of the controller's inputs onto a set of branch control inputs. The scheme presented in this paper makes use of the observation that in any given internal state of a controller, the actual number of different branches (next state/output pairs) is an extremely small fraction of the number of possible branches. Several circuit structures that implement the mapping are discussed, and examples presented to show that the cost of the mapping and selecting circuitry are small in relation to the resulting savings.