Terms Of Hardware Cost Research Articles

Computational methods to increase the speed of FPGA-based discrete wavelet transforms

The article considers the computational methods and features of the construction of a complex functional block for the implementation of the discrete wavelet transform (DWT) Dobeshie 9/7 in digital image signal processing systems based on FPGA. We proposed a mathematical model and algorithms for the implementation of parallel and series-convector methods of signal processing to calculate the coefficients of a discrete bi-orthogonal Dobeshie wavelet 9/7 taking into account the architecture of used FPGA. The model is based on wavelet transform factorization methods using lifting schemes. In contrast to conventional lifting schemes, the proposed method and algorithms can increase the speed of FPGA calculations with simplified hardware implementation. CAD Quartus II and ModelSim are used as a development environment. The behavioral model is written in Verilog HDL. Altera Cyclone® IV 4CE115 was used as FPGA. On the basis of the obtained behavioral model the testing module was developed and the simulation of digital circuit in the ModelSim environment was carried out. The formula for estimating the number of clock cycles of the forward and reverse DWT has been proposed; on its basis the estimate of the number of parallel computations depending on the number of input elements and the characteristics of the FPGA was obtained. As a result of experiments the dependences of the number of cycles for DWT computation depending on the size of the side of a square image with different variants of the number of parallel processing blocks were obtained. It is shown that parallel work of several independent modules gives a possibility to conduct concurrent processing of several input columns (rows) from input 2D array, and unification of the multiplier-summing module allows to increase efficiency of calculations and to reduce volume of occupied hardware resources. Conveyor based DWT structure is characterized by less hardware costs in terms of implementation of the calculator unit and memory allocation. As a result of testing the digital circuit, it was found that the developed block structure can significantly increase the DWT speed as well as reduce the cost of the system on a chip. The proposed realization of the block of two-dimensional forward and reverse wavelet transform for the Dobeshi 9/7 filter bank forms a complete module and can be used as a ready-made complex functional block for further development of high quality image transmission systems in real time.

METHOD OF LOW-RESOURCE HASHING TYPE "DATA – GENERATOR"

Creating a secure and efficient structure of a cryptographic algorithm is one of the key cryptographic tasks. Recently, cryptography for low-resource devices has attracted considerable attention of world scientists. A significant portion of the research is dedicated to the examination of block encryption methods, and conversely, there are notably fewer publicly disclosed proposals for low-resource hashing methods. Many hash functions recommended for use in low-resource devices by well-known standardization organizations are based on block encryption, which offers a sufficient level of security but demands substantial computational resources—something critical for their application in such devices. The urgency of investigating low-resource data hashing methods stems from the need to guarantee an adequate level of hash function security while minimizing computational resource usage through adjustments to the hashing process. This article reviews established approaches to constructing hash functions of varying complexities and examines the latest research and publications focused on low-resource hashing. Based on this, the structure and approach for developing a low-resource data hashing method were chosen. A novel low-resource hashing method, founded on the Merkle-Damgård construction and utilizing an iterative byte-oriented approach, is introduced. The process of low-resource hashing, according to the new method, is formally described. Statistical testing of the proposed method was conducted in accordance with NIST SP 800-22. An overview of the hardware implementation of the proposed low-resource hashing method is presented in the form of a generalized structural diagram. The complexity of the proposed hardware implementation is quantified in conventional units [GE] for hash value calculations of 128, 192, and 256 bits. A comparison of the proposed "data-generator" type hashing method with established low-resource hash functions, in terms of hardware costs, is conducted.

On the Lower Bound of Cost of MDS Matrices

Ever since lightweight cryptography emerged as one of the trending topics in symmetric key cryptography, optimizing the implementation cost of MDS matrices has been in the center of attention. In this direction, various metrics like d-XOR, s-XOR and g-XOR have been proposed to mimic the hardware cost. Consequently, efforts also have been made to search for the optimal MDS matrices for dimensions relevant to cryptographic applications according to these metrics. However, finding the optimal MDS matrix in terms of hardware cost still remains an unsolved problem. In this paper, we settle the question of the optimal 4 x 4 MDS matrices over GL(n, F2) under the recently proposed metric sequential XOR count based on words (sw-XOR). We prove that the sw-XOR of such matrices is at least 8n + 3, and the bound is tight as matrices with sw-XOR cost 35 and 67 for the values of n = 4 and 8, respectively, were already known. Moreover, the lower bound for these values of n matches with the known lower bounds according to s-XOR and g-XOR metrics.

Joint Altitude and Hybrid Beamspace Precoding Optimization for UAV-Enabled Multiuser mmWave MIMO System

The combination of unmanned aerial vehicles (UAVs) and millimeter wave (mmWave) multiple-input multiple-out (MIMO) system is regarded as a key enabling technology for beyond 5G networks, as it provides high data rate aerial links. However, establishing UAV-enabled mmWave MIMO communication is quite challenging due to the high hardware cost in terms of radio frequency (RF) chains. As a cost-effective alternative, a beamspace precoding with discrete lens arrays (DLA) architecture has received considerable attention. However, the underlying optimal design in beamspace precoding has not been fully exploited in UAV-enabled communication scenario. In this paper, the joint design of the UAV’s altitude and hybrid beamspace precoding is proposed for the UAV-enabled multiuser MIMO system, in which the DLA is exploited to reduce the number of the RF chain. In the proposed scheme, the optimization problem is formulated as a minimum weighted mean squared error (MWMSE) method. Then an efficient algorithm with the penalty dual decomposition (PDD) is proposed that aims to jointly optimize the altitude of UAV, beam selection and digital precoding matrices. Simulation results confirm the comparable performance of the proposed scheme and perform close to full-digital beamforming in terms of achievable spectral efficiency.

Cost Efficient Sensor Positions Determination For Human Activity Recognition

Human activity recognition(HAR) is one of the most active topics in the field of ubiquitous computing. Multi-sensor based HAR has attracted extensive interest because of its high recognition accuracy. Correspondingly, the number of body sensors in terms of hardware cost, the overload on communications, the storage and the computational complexity will be very high. In this paper, we propose a novel approach which can optimize cost-efficient sensors positions to save all the costs while maintaining high recognition performance. The tradeoff among the sensor positions, the target category, and the redundancy is considered. We also propose a data set D that contains acceleration sensor data for seventeen positions of the human body by simulating the worker actions in a factory assembly lines. The experimental results show that only six sensors can maintain high activity recognition accuracy out of seventeen sensors by using the proposed method.

On the Benefits of Using Object-Oriented Programming for the Objective Evaluation of Vehicle Dynamic Performance in Concurrent Simulations

Assessing passenger cars’ dynamic performance is a critical aspect for car industries, due to its impact on the overall vehicle safety evaluation and the subjective nature of the involved handling and comfort metrics. Accordingly, ISO standards, such as ISO 4138 and ISO 3888, define several specific driving tests to assess vehicle dynamics performance objectively. Consequently, proper evaluation of the dynamic behaviour requires measuring several physical quantities, including accelerations, speed, and linear and angular displacements obtained after instrumenting a vehicle with multiple sensors. This experimental activity is highly demanding in terms of hardware costs, and it is also significantly time-consuming. Several approaches can be considered for reducing vehicle development time. In particular, simulation software can be exploited to predict the approximate behaviour of a vehicle using virtual scenarios. Moreover, motion platforms and detail-scalable numerical vehicle models are widely implemented for the purpose. This paper focuses on a customized simulation environment developed in C++, which exploits the advantages of object-oriented programming. The presented framework strives to perform concurrent simulations of vehicles with different characteristics such as mass, tyres, engine, suspension, and transmission systems. Within the proposed simulation framework, we adopted a hierarchical and modular representation. Vehicles are modelled by a 14 degree-of-freedom (DOF) full-vehicle model, capable of capturing the dynamics and complemented by a set of scalable-detail models for the remaining sub-systems such as tyre, engine, and steering system. Furthermore, this paper proposes the usage of autonomous virtual drivers for a more objective evaluation of vehicle dynamic performances. Moreover, to further evaluate our simulator architecture’s efficiency and assess the achieved level of concurrency, we designed a benchmark able to analyse the scaling of the performances with respect to the number of different vehicles during the same simulation. Finally, the paper reports the proposed simulation environment’s scalability resulting from a set of different and varying driving scenarios.

Compressive Sensing-Based Low-Complexity Detector for GSSK-MIMO Systems

The generalized space shift keying (GSSK) technique proposed for massive MIMO systems has significant advantages in terms of hardware costs. However, the maximum likelihood (ML) detection for GSSK is computationally intractable. Consequently many suboptimal schemes with varying performance complexity trade-offs like compressive sensing (CS) detectors are proposed. Nevertheless, the existing CS detectors estimate the transmitted signal only by single-stage, which results in a decrease in detection performance. In order to solve this issue, we proposed a novel detection framework in this letter. Different from the existing CS detectors, the framework includes two stages: rough and precise selection. In the rough selection stage, the Euclidean distance criterion is employed instead of the traditional inner product operation to determine an optimized superset of active antenna indices. The precise selection stage performs a further traversal search over the superset acquired by the first stage to obtain the final indices. The simulation results illustrate that the performance of the proposed scheme can exhibit significant performance enhancement over the existing CS detectors while retaining the low complexity advantage.

RETRACTED ARTICLE: Analysis of security issues of cloud-based web applications

The Cloud computing is a powerful tool to optimize the cost in terms of hardware, controllable, utility to sharing the data, due to abovementioned features most of the organization switching their applications and services on the cloud. Cloud services offer secure and scalable services, but there is always some security problem when data have transmitted from a central storage server to a different cloud, personal and private data commitment increase risk of data confidentiality, integrity, availability, and authentication before one choose a vendor in the cloud or choose the cloud and move services in the cloud. This paper aims to resolve issues and provide the countermeasures relating to security issues in clouds based web applications. The vulnerability scores, its impact on confidentiality, integrity, availability, access complexity, and risk on assets calculated, and it observed most of the vulnerabilities identified during the scanning are related to security due to mis-configurations of web servers. The results analyzed for the vulnerability scores, vulnerabilities impact on confidentiality, integrity, availability, access complexity, and risk are analyzed description, and risk assessment. The countermeasures for each vulnerability based on the experimental results discussed.

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4 × 4, 8 × 8, 16 × 16 and 32 × 32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

Reduced hardware costs with software and hardware implementation of digital methods multistage discrete Fourier transform on programmable logic devices

Let us consider questions, which are connected to the research of terms of hardware and software implementation digital signal processing (DSP) methods. Theoretical basis of this research are methods of non-recursive difference of digital filtration with integer difference coefficients different orders of difference and methods of multistage discrete Fourier transform (DFT) based on such digital filtration. The purpose of the study is the research and formalization of necessary and sufficient condition of lowering hardware costs in hardware and software implementation of methods multistage DFT of digital signals on programmable logic devices (PLD). For reaching the research goal there are used methods of direct search and comparative analysis of results of such realization of methods of multi-stage DFT of digital multi-band signals, while filtering these signals, which are based on their non-recursive difference digital filtering with integer difference values coefficients and different orders of magnitude of difference. There are described abilities and specialties of PLD, which are built using architecture of a coarse-grained or fine-grained architecture or using combined architecture, which connects the convenience of implementing digital processing algorithms signals on the basis of tables of code conversion and reconfigurable memory modules. It is clear that a necessary and sufficient condition of lowering hardware costs in terms of hardware and software realization of methods for multi-stage DFT of digital signals on PLD is the triviality of meanings of integer difference coefficients of a non-recursive difference digital high difference orders’ filtration, which ensure this information. There is mentioned a formula, which allows making such condition. The practical significance of the research results consists of defining the necessary and sufficient condition of lowering hardware costs in terms of hardware and software implementation on PLD methods of multi-stage DFT signals based on their non-recursive digital difference filtering with integer values differential coefficients of various orders of magnitude difference. The novelty of research results lies in formalization of this condition. The reliability of the research results confirms their compliance with the results of well-known developments of DSP methods.

Design of Area Efficient Beam Steering Control System for Phased Array Radar

Phased array radar architecture consists of the multiple antenna elements that are controlled by the active electronic circuits called T/R modules. Transmit/Receive modules (T/R modules) plays vital role in the modern phased array radar system for different radar applications. The problem asserted with electrically scanned phased array radar suffers from two main limitations. First one is the high hardware cost in terms of area and second one is the design complexity. To overcome the above issues, architecture has been developed by implementing single control unit, distributive memory elements and data control logic to design an area efficient control system. The entire system is implemented on Artix-7 FPGA.

Tackling Biased PUFs Through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor

This paper presents an efficient fuzzy extractor (FE) design for biased physically unclonable functions (PUFs). To remove entropy leak from helper data in an efficient manner, we propose a new debiasing method, namely biased masking (BM). The proposed scheme removes the entropy leak by applying artificial noise (i.e., biased mask) such that the resulting response is uniform, and the added noise is removed by ECC decoding at the reconstruction as well as PUF noise. In addition, BM-based debiasing can be easily implemented with only additional random number generator and bit-parallel AND or OR operation in an enrollment server. Client devices with PUF, which are sometimes resource-constrained, require no additional operation. Furthermore, we show that the BM-based FE is reusable as well as the conventional code-offset FE. We evaluate the efficiency and effectiveness of the BM-based FE compared with the conventional debiasing-based FEs. Consequently, we confirm that the BM-based FE can achieve approximately 20 percent lower PUF size for nonnegligible biases (e.g., 60 percent) by just increasing the length of repetition code, which indicates that the BM-based FE is suitable for resource-constrained devices in terms of hardware cost for implementing PUF and computational cost at the reconstruction.

Workflow assessment as a preclinical development tool : Surgical process models of three techniques for minimally invasive cochlear implantation.

Minimally invasive cochlear implant surgery is a challenging procedure due to high demands on accuracy. For clinical success, an according assistance system has to compete against the traditional approach in terms of risk, operating time and cost. It has not yet been determined what kind of system is the most suited. The purpose of this study is a proof of concept of surgical process modeling as a preclinical development tool and the comparison of workflow concepts for this new approach. Three preclinical systems (two stereotactic and one robotic) for minimally invasive cochlear implant surgery are compared using the method of surgical process modeling. All three systems were successfully tested with ex vivo human specimen to create minimally invasive surgical access to the cochlea. Those systems where chosen for comparison, because they represent three diverse approaches with different corresponding workflows for the same intervention. The experiments were used to create a process model for each system by recording the interventions. All three conceptual systems developed by our group have shown their eligibility. The recorded process models provide a convenient method for direct comparison. Reduction in the surgical time has a higher impact on the process, than time that is needed for setting up a system beforehand. The stereotactic approaches have little preparation effort and are low cost in terms of hardware compared to the robotic approach, which in return is beneficial in terms of workload reduction for the surgeon. Surgical process modeling is suitable for comparison of different assistant systems for minimally invasive cochlear implantation. The benefit of reduced trauma, compared to the traditional mastoidectomy, can now be assessed with consideration of the workflow of each technique. The process models enable an assessment in the regard of surgical time and workload.

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for the Internet based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based security primitive and can be used to generate a key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs (CRPs). It is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This article first presents a new classification for RPUFs, namely circuit-based RPUF (C-RPUF) and algorithm-based RPUF (A-RPUF); two Exclusive OR (XOR)-based RPUF circuits (an XOR-based reconfigurable bistable ring PUF (XRBR PUF) and an XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented on Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The implementation results are compared with previous PUF designs and show good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response. This confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability.

Low‐complexity sparse detector for generalised space shift keying

Generalised space shift keying (GSSK) technique proposed for massive multi-input–multi-output systems has a higher information transmission rate due to the activation of multiple antennas at the same time, and also has significant advantage in terms of hardware cost. However, the maximum likelihood detector has a very high complexity which makes it computationally intractable for large-scale GSSK systems. In this Letter, a sparse detector is proposed by exploiting the inherent property of sparsity in GSSK. Different from the existing compressed sensing (CS)-based detectors, the proposed detector utilises Euclidean distance instead of inner product operation for antenna matching. Moreover, it can remove erroneous antenna indices by backtracking to promote the detection performance. The simulation results show that the proposed scheme outperforms the existing CS-based detectors while maintaining low complexity.

Fault Tolerant Dynamic Scheduling on Real Time Hierarchical System: Proposals for Fault Tolerant Mechanism on Safety-Critical System

The paradigm changes from federated architecture to integrated architecture in the real time system introduces a partitioned system to ensure fault isolation and for scheduling the hierarchy scheduling at the global level between partition and local in partition. Integrated architecture based on partitioned system with hierarchical scheduling is referred as real time hierarchical system which is a solution to increase efficiency in terms of hardware cost and size. This approach increasing the complexity of the integration process including the handling of faults. In this paper the authors describe a proposal with three components for dealing with fault tolerant in real time hierarchical systems by handling fault in task level, partition level and distributed level. The contribution of this proposal is the mechanism for building fault tolerant system on real time hierarchical system.

MCL: A Cost-Efficient Nonblocking Multicast Interconnection Network

Interconnection networks lie in the heart of all types of parallel architectures, because how processors or memory modules are connected to each other has a significant impact on the scalability, reliability, cost and performance. For example, a nonblocking interconnection network delivers guaranteed path availability to any connection requests, without interference to existing connections. Also, an interconnection network with multicast capability can distribute data from a single source to all the destinations in a one-shot manner, eliminating unnecessary duplications and minimizing communication delays. However, implementing nonblocking multicast networks imposes great challenges to designers because both of them demand high hardware cost. To deal with this problem, in this paper we propose a novel interconnection network, named Multicast Capable Low-cost Network (MCL) , which is both nonblocking for multicast traffic and cost-efficient. We first design the topologies and routing algorithms for MCL, and then prove its nonblocking multicast properties. Most importantly, we show that MCL achieves the lowest hardware cost in terms of asymptotic number of crosspoints. Specifically, the theoretical upper bound on the crosspoints of an $N \times N$ MCL is $O(N \log ^{3.39} N)$ . The explicitly constructed instance of an $N \times N$ MCL has a cost of $O(N^\frac{5}{4})$ and constant delay from the input ports to the output ports. These theoretical and practical costs are both the lowest compared to previous designs which deliver the same performance.

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design

A physical unclonable function (PUF) is a promising security primitive which utilizes the manufacturing process variations to generate a unique unclonable digital fingerprint for a chip. It is especially suitable for resource constrained security applications, e.g. internet of things (IoT) devices. The ring oscillator (RO) PUF and the static RAM (SRAM) PUF are two of the most extensively studied PUF designs. However, previous RO PUF designs require a lot of hardware resources for ROs to be robust and SRAM PUFs are not suitable for authentication. The previous research by the author proposed a tristate static RAM (TSRAM) PUF which is a highly fiexible challenge response pair (CRP) based SRAM PUF design. In this paper, a novel configurable PUF structure based on tristate inverters, namely a tristate configurable ring oscillator (TCRO) PUF is proposed. A configurable delay unit, composed of a tristate matrix, is used to replace the inverters in the RO PUF. The configurable bits are able to select a subset of the tristate inverters in the delay unit. Each tristate inverter is completely utilized by using the configurable delay unit and thus the approach enhances the flexibility and entropy of the proposed PUF design. The proposed PUF design can generate an exponential number of CRPs compared with the conventional RO PUF. Moreover, the proposed design significantly reduces the hardware resource consumption of the RO PUF. Delay models of both the TSRAM PUF and the proposed TCRO PUF designs are presented. A comprehensive evaluation of the TSRAM PUF is proceeded. To validate the proposed TSRAM PUF and TCRO PUF designs, a simulation based on UMC 65nm technology and a hardware implementation on a Xilinx Virtex-II FPGA are presented. The experimental results demonstrate good uniqueness and reliability as well as high efficiency in terms of hardware cost.

Adaptability Analysis for IP Switching and Optical Switching in Geographically Distributed Inter-Datacenter Networks

The unexpected growth of cloud services lead to a dramatic increase in the network capital expenditure (CAPEX) and latency in geographically distributed inter-datacenter networks. In this paper, an adaptability analysis is proposed on CAPEX and forwarding delay for IP switching and optical transport network (OTN) switching in distributed inter-datacenter networks. By abstracting the switching behavior of the IP routers and OTN equipment, the IP nodes, and OTN nodes are mapped to the switching matrix of CLOS switching network. A unified network-level connection model is established based on CLOS switching network to meet the needs of connectivity. Then, the hardware costs and the forwarding delay are evaluated to find out the bandwidth threshold (BDT) which decides the most suitable switching mode for a specific switching granularity. The adaptability of IP switching and OTN switching under different switching granularities and port rates is performed based on the simulation platform in terms of hardware cost, optical port cost, and forwarding delay. Simulation results show that the BDT based on hardware cost is 280 Mbps when switching granularity is 1.25 Gb/s. For 2.5 Gb/s switching granularity, when average bandwidth between multiple datacenters is higher than 600 Mbps, OTN switching has more advantages than IP switching on capital expenditure, especially when port rate of the equipment is high. In addition, the simulation results also verify that the forwarding delay is reduced obviously with OTN switching.

Combining ML and Compressive Sensing: Detection Schemes for Generalized Space Shift Keying

Generalized space shift keying (GSSK) proposed for large scale MIMO systems promises significant advantages in terms of hardware costs. However, the maximum likelihood (ML) detection for GSSK is computationally intractable. Detection schemes using compressive sensing (CS) offer a favorable performance-complexity tradeoff. In this letter, we propose a novel GSSK detection framework, where CS algorithms are used to reduce the complexity of ML detection. The proposed framework significantly reduces the performance gap between existing CS-based detection schemes and ML detection while retaining the complexity advantage of CS algorithms. Simulation results demonstrate the superiority of proposed scheme over popular CS-based detection schemes.