Ten-year Data Retention Research Articles

The Effect of Sputtering Sequence Engineering in Superlattice-like Sb-Rich-Based Phase Change Materials.

This paper presents a comprehensive investigation into the thermal stability of superlattice-like (SLL) thin films fabricated by varying the sputtering sequences of the SLL [Ge8Sb92(25nm)/GeTe(25nm)]1 and SLL [GeTe(25nm)/Ge8Sb92(25nm)]1 configurations. Our results reveal significantly enhanced ten-year data retention (Tten) for both thin films measured at 124.3 °C and 151.9 °C, respectively. These values surpass the Tten of Ge2Sb2Te5 (85 °C), clearly demonstrating the superior thermal stability of the studied SLL configurations. Interestingly, we also observe a distinct difference in the thermal stability between the two SLL configurations. The superior thermal stability of SLL [GeTe(25nm)/Ge8Sb92(25nm)]1 is attributed to the diffusion of the Sb precipitated phase from Ge8Sb92 to GeTe. This diffusion process effectively reduces the impact of the Sb phase on the thermal stability of the thin film. In contrast, in the case of SLL [Ge8Sb92(25nm)/GeTe(25nm)]1, the presence of the Sb precipitated phase in Ge8Sb92 facilitates the crystallization of GeTe, leading to reduced thermal stability. These findings underscore the significant influence of the sputtering sequence on the atomic behavior and thermal properties of superlattice-like phase change materials. Such insights provide a robust foundation for the design and exploration of novel phase change materials with improved thermal performance.

Multilevel optoelectronic hybrid memory based on N-doped Ge2Sb2Te5 film with low resistance drift and ultrafast speed

Multilevel phase-change memory is an attractive technology to increase storage capacity and density owing to its high-speed, scalable and non-volatile characteristics. However, the contradiction between thermal stability and operation speed is one of key factors to restrain the development of phase-change memory. Here, N-doped Ge2Sb2Te5-based optoelectronic hybrid memory is proposed to simultaneously implement high thermal stability and ultrafast operation speed. The picosecond laser is adopted to write/erase information based on reversible phase transition characteristics whereas the resistance is detected to perform information readout. Results show that when N content is 27.4 at.%, N-doped Ge2Sb2Te5 film possesses high ten-year data retention temperature of 175 °C and low resistance drift coefficient of 0.00024 at 85 °C, 0.00170 at 120 °C, and 0.00249 at 150 °C, respectively, owing to the formation of Ge–N, Sb–N, and Te–N bonds. The SET/RESET operation speeds of the film reach 520 ps/13 ps. In parallel, the reversible switching cycle of the corresponding device is realized with the resistance ratio of three orders of magnitude. Four-level reversible resistance states induced by various crystallization degrees are also obtained together with low resistance drift coefficients. Therefore, the N-doped Ge2Sb2Te5 thin film is a promising phase-change material for ultrafast multilevel optoelectronic hybrid storage.

Designing Sb phase change materials by alloying with Ga2S3 towards high thermal stability and low resistance drift by bond reconfigurations

The pure Sb phase-change thin films alloyed with Ga2S3 alloy have been prepared and the related properties have been investigated. Compared with pure Sb, Ga2S3-alloyed Sb films exhibit higher crystallization temperature (∼250 °C), larger ten-year data retention temperature (∼166 °C), and higher crystallization activation energy (4.10 eV). These thermal parameters indicate that the thermal stability of the Ga2S3-alloyed Sb thin films can be considerably enhanced due to the formation of high binding energy Sb-S and Sb-Ga bonds. Moreover, the enhanced thermal stability can also significantly lower resistance drift coefficient (0.0014). According to the analysis of the crystallization mechanism, the crystallization kinetic index (n) is determined to be 0.625, implying one-dimensional growth type in Ga2S3-alloyed Sb thin films. This can benefit to reduce the nucleation randomness and decrease resistance drift. The work demonstrates that Ga2S3-alloyed Sb materials have excellent potential for embedded memory applications.

GeTe/CrSb2Te superlattice-like thin film for excellent thermal stability and high phase change speed

Thermal stability and operation speed are two key challenges in phase change memory (PCM). This work reports GeTe/Cr0.16Sb2Te (GT/CrST) superlattice-like (SLL) films for both high operation speed and superior thermal stability. The thermal properties, phase change behaviors, microstructural evolution and the electrical performances are investigated in detail. Results show that [GT(8 nm)/CrST(2 nm)]7 film possesses excellent ten-year data-retention (T10-year=156 ºC), small density change rate (2.6%), ultrafast reversible phase change (0.5 ns), and low resistance drift coefficient (∼0.07). Furthermore, the [GT(8 nm)/CrST(2 nm)]7 based PCM cell has the reversible operation time of as low as 8 ns and low power consumption of 8.1×10−12 J. The two-dimensional finite element analysis confirms that the lower power consumption is ascribed to the existence of interfacial thermal resistance in SLL thin film, leading to the lower thermal conductivity. Results indicate that [GT(8 nm)/CrST(2 nm)]7 thin film has great potential for PCM application with excellent thermal stability and phase change speed.

Rules of hierarchical melt and coordinate bond to design crystallization in doped phase change materials

While alloy design has practically shown an efficient strategy to mediate two seemingly conflicted performances of writing speed and data retention in phase-change memory, the detailed kinetic pathway of alloy-tuned crystallization is still unclear. Here, we propose hierarchical melt and coordinate bond strategies to solve them, where the former stabilizes a medium-range crystal-like region and the latter provides a rule to stabilize amorphous. The Er0.52Sb2Te3 compound we designed achieves writing speed of 3.2 ns and ten-year data retention of 161 °C. We provide a direct atomic-level evidence that two neighbor Er atoms stabilize a medium-range crystal-like region, acting as a precursor to accelerate crystallization; meanwhile, the stabilized amorphous originates from the formation of coordinate bonds by sharing lone-pair electrons of chalcogenide atoms with the empty 5d orbitals of Er atoms. The two rules pave the way for the development of storage-class memory with comprehensive performance to achieve next technological node.

Simultaneously good thermal stability and low power consumption for Sb/In48.9Sb15.5Te35.6 multilayer composite film

Thermal stability and power consumption were two important problems to be solved in the development of phase change memory. In this paper, Sb/In48.9Sb15.5Te35.6 multilayer phase change thin films were prepared by magnetron sputtering, and their comprehensive properties were systematically studied. In-situ heating was employed to study the transition process of Sb/ In48.9Sb15.5Te35.6 multilayer films from amorphous to crystalline state. The ten-year data retention ability was evaluated by isothermal crystallization method. The change of band gap energy was measured by near infrared spectrophotometer. X-ray diffraction and Raman spectroscopy were used to study the change of phase structure at different annealing temperatures. The surface morphology of thin films at different annealing temperatures was observed by atomic force microscope. The device based on [Sb(5 nm)/In48.9Sb15.5Te35.6(5 nm)]8 had a small threshold voltage. The results showed that Sb/In48.9Sb15.5Te35.6 multilayer composite film was a potential phase change material with good thermal stability and low power consumption.

Impact of the Nonlinear Dielectric Hysteresis Properties of a Charge Trap Layer in a Novel Hybrid High-Speed and Low-Power Ferroelectric or Antiferroelectric HSO/HZO Boosted Charge Trap Memory

A novel hybrid antiferroelectric (AFE)-based charge trap (CT) memory is reported focusing on an amplified tunnel oxide field ( ${E} _{\text {TO}}$ ) via the dynamic of an AFE hysteresis dipole switching. The role of dynamic permittivity increase and the saturated polarization at the instant of the write operation are explored for enhanced ${E} _{\text {TO}}$ . The hybrid CT concept is studied by benchmarking the controlled properties of the HfO2 CT layer via the Si elemental doping in order to stabilize the linear dielectric (DE), ferroelectric (FE), or AFE response. The Si-doped HfO2 (HSO) with AFE stabilized phase shows the largest memory window (4.5 V) compared to the DE- or FE-based CT layers. The dynamic AFE dipole switching enables a maximized ${E} _{\text {TO}}$ at the instant of switching such that a high-speed and low-power CT memory is realized. The role of the tailored hysteresis shape on the ${E} _{\text {TO}}$ magnitude is studied for different Si contents and benchmarked to the Zr-doped hafnium oxide (HZO). The AFE CT multilevel coding as 1–3 bit/cell, the role of the pass voltage disturb, and a mini-NAND array operation are demonstrated. The global variability and area scalability of the HSO CT devices are studied to indicate the effect of Si content distribution and the area dependence of the AFE film variability. AFE CT devices are characterized for a switching speed ( $ ), ten-year data retention, and $10^{{5}}$ endurance. Moreover, the improved CT characteristics by the AFE dipole switching are explored for enhanced long-term potentiation and depression of a synaptic device.

Tunable crystallization mechanism of Sb4Te films by VO2 nano-grid framework for breaking through the trade-off between thermal stability and crystallization speed

The thermal stability and optical bandgap of the amorphous Sb4Te film can be improved significantly by combining with VO2, which leads to a high crystallization temperature (around 220 °C), good data retention (ten-year data retention above 130 °C), and high amorphous resistance. The crystallization mechanism of Sb4Te changes from growth-dominated mode into nucleation-dominate one, which is confirmed by in situ microstructure observation experimentally and crystallization kinetics index theoretically, due to the long-range orders of Sb–Te and Sb–Sb bonds disorganized by the introduction of VO2 nano-grid framework. The Sb4Te crystallites can be refined and confined in the VO2 nano-grid framework. VO2–Sb4Te films with less than 15 at.% of VO2 maintain the high crystallization speed. The nano-grid framework of VO2 enables an efficient way to invade the long-order bonds of Sb4Te, which improves the rigid trade-off between thermal stability and crystallization speed. It provides a novel clue for optimizing other phase-change materials.

Resistive switching characteristics of a modified active electrode and Ti buffer layer in Cu[sbnd]Se-based atomic switch

Atomic switches are well-known promising candidates for future application in non-volatile logic memory devices. The resistive switching characteristics of these devices depend on the formation of a conductive filament (CF) by active metal electrodes. However, the formation of a stable CF is still a challenge owing to filament overgrowth in the solid electrolyte. To achieve controlled CF growth, we have used a modified active electrode with different CuxSe1−x composition ratios (0.01 < x < 0.45) and a titanium (Ti) buffer layer. The optimum composition was determined to be Cu0.11Se0.89/Ti (2.5 nm) for which excellent resistive switching properties were observed, such as a high on/off ratio of 104, low operating voltage, uniform resistance distribution, ten-year data retention at 85 °C, and uniform endurance (2000 cycles). The improvement is can be described from the high controllability of the oxidation-reduction reaction rate of the optimized CuSe modified active electrode by the means of Ti buffer layer and the TiO bond formation at the Ti/Al2O3 interface. In addition, depth profiles of the conductive filament based on Cu0.11Se0.89 with a Ti buffer layer were studied by performing current atomic force microscopy (I-AFM) to evaluate the enhancements in electrical performance and reliability resulting from the insertion of the Ti buffer layer.

Se-doped Ge10Sb90 for highly reliable phase-change memory with low operation power

Abstract

Performance Enhancement of Silicon Nanowire Memory by Tunnel Oxynitride, Stacked Charge Trap Layer, and Mechanical Strain

Heavily doped silicon nanowires (SiNWs) are adopted to fabricate a memory device composed of an AlON tunnel layer and a HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfAlO charge trap bilayer, which exhibits a large memory window of 4.6 V when operated in the program/erase phases, i.e., +12 V for 100 μs and -12 V for 10 ms, along with excellent 70% extrapolated ten-year data retention and good endurance up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> cycles. Strain effects on SiNW memory characteristics have also been investigated. It is demonstrated that the tensile strain increases the program window and the compressive strain improves the data retention. The underlying mechanism is attributed to the incorporation of nitrogen in the AlON tunnel layer.

High-Speed Multilevel nand Flash Memory With Tight $V_{\rm th}$ Distribution Using an Engineered Potential Well and Forward-Bias Adjusted Programming

This paper reports a high-speed multilevel-cell nand Flash memory device using a Si- SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TiN- TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -TaN (SOTTOT) engineered potential well (EW). The SOTTOT EW Flash memory device has very fast cell programming speed and good data retention. A 16-kbit nand memory block using SOTTOT cells was programmed using a forward-bias-adjusted programming scheme, which enables bit adjustability during page programming to suppress the development of fast bits. The SOTTOT memory block shows fast programming speed (~40 μs/page), tight threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) distribution (~0.22 V/level), and clear <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -level margins (~0.9 V) for the eight-level programming. The SOTTOT memory block also shows good resistance against pass/read disturbances as well as good ten-year data retention at an ambient temperature of 75 °C throughout 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> programming/erasing cycling.

Phase-Change Memory Devices Operative at 100 $^{\circ} \hbox{C}$

Phase-change memory (PCM), although promising operative at room temperature, is struggling to achieve ten-year data retention over 100°C. We disclose here that a PCM device made of the composition Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">25</sub> Te <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">67</sub> exhibits normal operation at 100°C for an endurance of at least 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> cycles. At room temperature, the endurance is at least 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> cycles. The set-reset speed of the devices reaches 20 ns, and the reset current is around 20% less than that of our reference test cells made of the benchmark Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> .

Nanocomposite Phase-Change Memory Alloys for Very High Temperature Data Retention

Phase-change memory alloys based on germanium, antimony, and tellurium with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanophase dielectric inclusions are investigated for material and electrical properties. The new alloys are prepared by cosputtering with a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> target creating nanophase dielectric inclusions. The addition of the dielectric inclusions significantly increases the crystallization temperature without affecting the required programming current. In memory device configurations, the nanocomposite alloys exhibit a ten-year data retention above 200°C and a cycle life greater than 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles while maintaining the SET programming speed of 250 ns.

Tunnel Barrier Engineering for Non-Volatile Memory

Tunnel oxide of non-volatile memory (NVM) devices would be very difficult to downscale if ten-year data retention were still needed. This requirement limits further improvement of device performance in terms of programming speed and operating voltages. Consequently, for low-power applications with Fowler-Nordheim programming such as NAND, program and erase voltages are essentially sustained at unacceptably high levels. A promising solution for tunnel oxide scaling is tunnel barrier engineering (TBE), which uses multiple dielectric stacks to enhance field-sensitivity. This allows for shorter writing/erasing times and/or lower operating voltages than single SiO₂ tunnel oxide without altering the ten-year data retention constraint. In this paper, two approaches for tunnel barrier engineering are compared: the crested barrier and variable oxide thickness. Key results of TBE and its applications for NVM are also addressed.

Yield and reliability of MNOS EEPROM products

MNOS electrically erasable and programmable read-only memory (EEPROM) products have been manufactured using 2- mu m CMOS fabrication technology, in which MNOS memory devices are composed of a 1.6-nm tunnel SiO/sub 2/ layer and a 28-nm Si/sub 3/N/sub 4/ layer. The Hitachi MNOS EEPROM family consists of a 64-kb EEPROM with static random access memory (SRAM) timing and three EEPROM on-chip microcomputers. Electrical and quality tests establish two basic reliability features: ten-year data retention and 10/sup 5/ erase/write cycle endurance. The MNOS EEPROM family yield has reached the same high level as that of SRAM products fabricated with the same 2- mu m CMOS technology. In addition, high-density low-cost MNOS EEPROM products are possible because of the high scalability and high yield attributable to their simple cell structure. >