Wafer Level Packaging Technology Research Articles

Wafer-level hermetic vacuum packaging by bonding with a copper–tin thin film sealing ring

A wafer-level hermetic vacuum packaging technology intended for use with MEMS devices was developed based on a copper–tin (CuSn) thin film sealing ring. To allow hermetic packaging, the shear strength of the CuSn thin film bond was improved by optimizing the pretreatment conditions. As a result, an average shear strength of 72.3 MPa was obtained and a cavity that had been hermetically sealed using wafer-level packaging (WLP) maintained its vacuum for 1.84 years. The total pressures in the cavities and the partial pressures of residual gases were directly determined with an ultra-low outgassing residual gas analyzer (RGA) system. Hermeticity was evaluated based on helium leak rates, which were calculated from helium pressures determined with the RGA system. The resulting data showed that a vacuum cavity following 1.84 years storage had a total pressure of 83.1 Pa, contained argon as the main residual gas and exhibited a helium leak rate as low as 1.67 × 10−17 Pa · m3 s−1, corresponding to an air leak rate of 6.19 × 10−18 Pa · m3 s−1. The RGA data demonstrate that WLP using a CuSn thin film sealing ring permits ultra-high hermeticity in conjunction with long-term vacuum packaging that is applicable to MEMS devices.

システムインテグレーションを実現するFO-WLPの最新実装技術とその将来展望

システムインテグレーションを実現するFO-WLPの最新実装技術とその将来展望

Integrated Systems-in-Package: Heterogeneous Integration of Millimeter-Wave Active Circuits and Passives in Fan-Out Wafer-Level Packaging Technologies

Recent advances in silicon semiconductor technology with transit and maximum oscillation frequencies above 300 GHz have enabled the integration of complex transceiver front ends operating in the millimeter-wave (mmW) regime for a variety of applications. Among these, the most prominent frequency ranges (and their associated applications) are currently the 60-GHz short-range communication frequency band [1]-[2] and E-band wireless back-haul solutions [3]-[4], as well as the 76-81-GHz band for automotive radar sensor realizations [5]-[6].

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

Characterizations of Fan-out Wafer-Level Packaging

Abstract The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.

A Fully Integrated Dual-Band WLP CMOS Power Amplifier for 802.11n WLAN Applications

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing

Advanced wafer-level packaging (WLP) techniques, mainly driven by high-performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology have been widely studied and developed over the last decade for use in various WLP technologies, such as package on package, fan-out integration, and 2.5-D and 3-D integration using through-silicon-via. Temporary bonding technology enables handling of thinned substrates (<100 μm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics was developed for temporary wafer bonding applications. These materials target high-temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (<5 μm) after grinding and have successfully passed a 200°C plasma-enhanced chemical vapor deposition (PECVD) process without any delamination during grinding and PECVD processes.

FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution

The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.

Integration of MEMS in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)

The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/Intel's eWLB technology, aiming to overcome the current limits for MEMS/Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.

Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes

The growing and diversifying system requirements have continued to drive the development of a variety of new package technologies and configurations: small form factor, low weight, low profile, high pin count and high speed and low cost. Embedded chip in EMC, also called fan-out wafer-level packaging (FOWLP), has been used in various products such as baseband, RF (radio frequency) transceiver, and PMICs (power management ICs). Currently, INFO technology developed by TSMC®, NANIUM® were in mass production for 3D integration for processor and memory, which inspires other packaging foundries to develop their own embedded FOWLP for the forecasted explosive growth of this market in the next few years. There are a number of challenges for FOWLP. For process point of view, temporary bonding and de-bonding are required. EMC wafers are difficult to handle due to its large warpage driven by the big CTE difference between the Si and molding material. In addition, the manufacturing of fine pitch RDL on EMC surface is also difficult. In this paper, the concept of wafer level embedded Si Fan-Out (eSiFO) technology was introduced and the development progress was reported. For eSiFO, cavities with certain depth were formed by Si dry etch. Then device dies were thinned to designed thickness. The dice were then placed into the cavities and bonded by the attached film on the bottom of the dice. A reconstructed wafer was formed. The micro gap between the chip and sidewall of the cavity as well as the surface of the reconstructed wafer were filled by dry film using vacuum process. Next, the pads were opened, followed RDL fabrication, repassivation, BGA, wafer thinning and dicing. Finally, an eSiFO package was fabricated. There are a number of advantages for eSiFO technology. There is nearly no warpage since the Si was used as reconstruct substrate. The process is relatively simple since no molding, temporary bonding and de-bonding are required. RDL manufacturing is easier on Si wafer vs with molding compounds and can achieve high density routing. Furthermore, it can provide small form factor since the thinning of wafer is the last step. To prove the concept of eSiFO, a 3.3 x 3.3mm package with 50 BGA bumps at 400μm pitch was fabricated. The device wafer was thinned to 100μm. The die size is 1.96 × 2.36mm with pad pitch at about 90μm. The depth of the cavities on 8 in. wafer formed by Bosch process on bare Si wafer was 107μm with 8μm variation. The length and width of Si cavities is 20μm larger than die size. In the package, there is one layer Cu RDL with thickness of 3μm, minimum line width of 13.72μm. The BGA ball diameter is 280μm. All the processes were evaluated and the results showed such packages can be produced. Reliability tests including THS, T/C, HTS and HAST were carried out and no failure issue was observed. Mechanical simulation was used to analyze the stress distribution during TC test and the results showed the maximum stress was located at the RDL near the UBM. In summary, a low cost wafer level fan out technology using reconstructed Si wafer was developed. The process is simple without molding, temporary bonding and de-bonding. The reliability tests of test vehicles proved that such package is reliable. The newly developed eSiFO technology can be widely used for chips requiring fan-Out, small form factor and high density interconnects.

Wafer-level hermetic thermo-compression bonding using electroplated gold sealing frame planarized by fly-cutting

In this paper, a novel wafer-level hermetic packaging technology for heterogeneous device integration is presented. Hermetic sealing is achieved by low-temperature thermo-compression bonding using electroplated Au micro-sealing frame planarized by single-point diamond fly-cutting. The proposed technology has significant advantages compared to other established processes in terms of integration of micro-structured wafer, vacuum encapsulation and electrical interconnection, which can be achieved at the same time. Furthermore, the technology is also achievable for a bonding frame width as narrow as 30 μm, giving it an advantage from a geometry perspective, and bonding temperatures as low as 300 °C, making it advantageous for temperature-sensitive devices. Outgassing in vacuum sealed cavities is studied and a cavity pressure below 500 Pa is achieved by introducing annealing steps prior to bonding. The pressure of the sealed cavity is measured by zero-balance method utilizing diaphragm-structured bonding test devices. The leak rate into the packages is determined by long-term sealed cavity pressure measurement for 1500 h to be less than Pa m3s−1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

Temporary Wafer Bonding Materials with Mechanical and Laser Debonding Technologies for Semiconductor Device Processing

Abstract Advanced wafer-level packaging (WLP) techniques, mainly driven by high performance applications in memory and mobile market, have been adopted for large-scale manufacturing in recent years. Temporary wafer bonding and debonding technology has been widely studied and developed over the last decade for use in various WLP technologies, such as package-on-package (PoP), fan-out integration, and 2.5-D and 3-D integration using through-silicon-via (TSV). Temporary bonding technology enables handling of thinned substrates (<100 μm), which can no longer self-support during backside processing and packaging. Moreover, some applications require the temporary bonding materials to withstand temperatures up to 250°C in high-vacuum conditions, and even up to 350°C or higher during the dopant activation step required for manufacturing power devices. Therefore, a simple yet effective temporary bonding process and material that can survive all the backside processes is highly desired. In this study, a series of formulations based on polar thermoplastics were developed for temporary wafer bonding applications. These materials target high temperature survivability and improved adhesion to prevent the premature delamination during downstream wafer processing. All of these materials provide high thermal stability up to 250°C or higher, and are able to be bonded to carrier wafers treated with release layers, which can be selectively debonded by either mechanical or laser release after backside processing. The material left on device wafer after debonding can be easily cleaned using common industrial solvents. Wafers bonded with these materials demonstrate lower overall stack total thickness variation (TTV < 5 μm) after grinding and have successfully passed a 200°C PECVD process without any delamination during grinding and PECVD processes.

Package Thickness - Ultrathin WLFO (Wafer-Level Fan-Out)

Abstract NANIUM's Fan-Out Wafer-Level Packaging technology WLFO (Wafer-Level Fan-Out) is based on embedded Wafer-Level Ball Grid Array technology eWLB of Infineon Technologies [1]. Since it′s invention almost 10 years ago, it became the leading technology for Fan-Out Wafer-Level packages. The WLFO technology is based upon the reconstitution of KGD (known good die) from incoming device wafer, independent of wafer diameter and material, to recon wafer format of active semiconductor dies or other active/passive components separated by mold compound applied through compression molding on a temporary mold carrier. The resulting recon wafer can be processed in standard wafer processing equipment. One of the challenges for the future of semiconductor packaging is reduction of the board level volume real estate occupied by each component. With the drive towards lower profile end user devices incorporating large display area and battery life the three dimensional space available for semiconductor packages is diminishing. It is well known that WLFO single die packaging but even more significant system integration enables the shrinkage of the XY footprint of the package through flexible very dense heterogeneous system-in-package integration [2]. But one of the disruptive advantages of the substrate-less WLFO technology is to also permit significant reduction of the overall package height (Z). A total package height for a BGA package including solder balls <500um and for a LGA package with solder land pads only <300um is achievable today, and further development towards even thinner packages is on the way.

High performance suspended spiral inductor and band-pass filter by wafer level packaging technology

Suspended inductors and 2.45 GHz BPF with patterned ground shields on the lossy silicon substrate by using Cu/BCB based wafer level packaging and bulk Si etching technologies were fabricated. Thick BCB interlayer is used as the supporting dielectric and the backside cavity is easily removed by using a two-step back-etching process. The fabricated 2.7 nH inductor has a maximum Q factor 49 at 8.2 GHz and high Q factors more than 22 in the broadband frequency range from 1 to 10 GHz. And the realized 2.45 GHz BPF has the insertion loss of 3.0 dB and the return loss of more than 14 dB at the pass band. It is also featured by more than 48 and 25 dB attenuation at 0.9 and 1.8 GHz respectively, with the second harmonic rejection being 33 dB.

Wafer-Level Hermetic All-Glass Packaging for Microalkali Vapor Cells of Chip-Scale Atomic Devices

To maintain a controllable environment for microalkali vapor cells of high-performance chip-scale atomic devices, a novel wafer-level hermetic all-glass packaging technology for microalkali vapor cells of atomic devices was investigated. A glass wafer with metal vias was used as the substrate to host the miroalkali vapor cells. Wafer-level hemispherical glass bubbles prepared by a chemical foaming process were used as transparent packaging caps. The performance of the rubidium vapor cell in the all-glass hermetic package was characterized by a laser frequency locking system and an ultraviolet spectrophotometer. The results show that hermetic all-glass packaging at a wafer level was demonstrated successfully. The results also indicate that after the hermetic all-glass packaging, the temperature variation of the microalkali vapor cells was controllably below 0.2 °C at different working temperatures of atomic devices. A chip-scale atomic magnetometer using the hermetic all-glass micro vapor cell was demonstrated eventually.

A Study on the Analysis of Optimal Design for Wafer Level Package According to Wafer Size

Recently the wafer size migration from 12 (300 mm) to 18 (450 mm) for the industry cost reduction can be achieved. Because it requires better thin film deposition property and the larger process compatibility. Wafer level package technology is added to the surface of wafer circuit packages to create a semiconductor technology that can minimize the size of the package. However, in conventional packaging, warpage and crack are major concerns for semiconductor manufacturing. We optimized the 12” and 18” wafer dam design using a finite element method according to the dam height and heat distribution thermal properties. The dam design influences the uniform deposition of the image sensor and prevents the filling material from overflowing. In this study, finite element analysis was employed to determine the key factors that may affect the reliability performance of the dam package. Three-dimensional finite element models were constructed using the simulation software ANSYS to perform the dam thermo-mechanical simulation and analysis.

Investigation of silicon-based light emitting diode sub-mounts: Enhanced performance and potential for improved reliability

Aluminum nitride (AlN) and aluminum oxide (Al2O3) ceramic light emitting diode (LED) sub-mounts are the most widely used package substrate for recently-developed high-brightness (HB) LED package applications because they exhibit superior thermal conductivity compared to conventional printed circuit board (PCB) package substrates. Nonetheless, the Al2O3 ceramic sub-mount exhibits thermal conductivity in an unacceptable range, and manufacturing the AlN ceramic sub-mount is problematic due to high material cost and difficult processing. Wafer-level packaging (WLP) technology has shown noticeable improvements in manufacturing and silicon exhibits outstanding thermal conductivity. Thus silicon might become an alternative package substrate for HB LEDs. This research studied the feasibility of replacing conventional ceramic sub-mounts with WLP LED sub-mounts. The performance features of thermal dissipation, insulation, and high temperature reliability of LED sub-mounts with variable SiO2 thickness were analyzed and compared to the results obtained from conventional Al2O3 and AlN ceramic sub-mounts. Experimental results show that silicon LED sub-mounts lead to better thermal dissipation performance than do Al2O3 ceramic sub-mounts, and the results also reveal acceptable insulation performance and high temperature reliability for silicon sub-mounts.

Wafer-level Au–Au bonding in the 350–450 °C temperature range

Metal thermocompression bonding is a hermetic wafer-level packaging technology that facilitates vertical integration and shrinks the area used for device sealing. In this paper, Au–Au bonding at 350, 400 and 450 °C has been investigated, bonding wafers with 1 µm Au on top of 200 nm TiW. Test Si laminates with device sealing frames of 100, 200, and 400 µm in width were realized. Bond strengths measured by pull tests ranged from 8 to 102 MPa and showed that the bond strength increased with higher bonding temperatures and decreased with increasing frame width. Effects of eutectic reactions, grain growth in the Au film and stress relaxation causing buckles in the TiW film were most pronounced at 450 °C and negligible at 350 °C. Bond temperature below the Au–Si eutectic temperature 363 °C is recommended.

공정시간 및 온도에 따른 웨이퍼레벨 패키지 접합 최적설계에 관한 연구

Article history: Wafer level package technology is added to the surface of wafer circuit packages to create a semiconductor technology that can minimize the size of the package. However, in conventional packaging, warpage and fracture are major concerns for semiconductor manufacturing. We optimized the wafer dam design using a finite element method according to the dam height and heat distribution thermal properties. The dam design influences the uniform deposition of the image sensor and prevents the filling material from overflowing. In this study, finite element analysis was employed to determine the key factors that may affect the reliability performance of the dam package. Three-dimensional finite element models were constructed using the simulation software ANSYS to perform the dam thermo-mechanical simulation and analysis.

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated circuit fabrication process and the market demands for devices with high electrical performance, small form factor, low cost etc. This paper reviews the advances of WLP technology in recent years. An overall introduction to WLP is presented in the first part. The fabrication processes of WLP and redistribution technology are introduced in the second part. Reliability problems of WLPs, such as the strength of solder joints and reliability problems concerning fan-out WLPs are introduced in the third part. Typical applications of WLP technologies are discussed in the last part, which include the application of fan-out WLP, 3D packaging integrating with WLP technologies and its application in microelectromechanical systems (MEMS).