Technology Computer-aided Design Research Articles

Simulation of Normally-Off Vertical GaN MOSFET with a Novel Enhanced Sidewall Channel by Selective Area Growth

In the present study, a novel normally-off vertical GaN MOSFET with an enhanced AlGaN/GaN channel on the sidewall has been proposed using the technology computer-aided design (TCAD) simulation. By using the selective area growth process, the trench structure and the enhanced sidewall channel are formed simultaneously, which is beneficial to enhance the conduction capability compared with the conventional trenched MOSFET. It demonstrates that a proper hole concentration and thickness of the p-GaN layer are key parameters to balance the threshold voltage, on-state resistance, and off-state breakdown voltage, resulting in the highest Baliga’s figure of merit value. Furthermore, a p-GaN shield layer is also adopted as a junction termination extension to modulate the electric field around the trench bottom. By optimizing the device parameters, a normally-off GaN MOSFET with good performance is designed.

Modeling of Composition and Channel Length-Dependent Transient Characteristics in Short-Channel IGZO Field-Effect Transistors.

In this study, we analyze the characteristics of fast transient drain current (ID) in IGZO-based field-effect transistors (FETs) with different composition ratios (device O: ratio of 1:1:1 for In, Ga, Zn, device G: ratio of 0.307:0.39:0.303) for reliable operations. Overshoot currents, which can cause device degradation, are caused by fast transients and are attributed to the trapping of electrons in the energy band. As the lateral electric field (Elat) of the IGZO channel is increased, the overshoot drain current difference (ΔIOS) is increased for both devices. It is also found that the increase in ΔIOS with decreasing L is less pronounced in device G compared with that for device O. While device G yields larger ΔIOS values than device O in long channels (L = 5, 10 μm), it yields smaller ΔIOS in short channels (L = 0.5, 1 μm). This phenomenon is explained using three physical parameters (nOS, Ever, and NOT), based on Technology Computer-Aided Design (TCAD) simulation modeling. Device G has stronger immunity against ΔIOS in a short-channel region; this can be attributed to the lower concentration of oxygen vacancies in device G that suppresses dopant diffusion effects within IGZO layer. These results experimentally demonstrate that the short-channel effects on fast-transient ID can be improved by controlling the Ga composition ratio of IGZO.

Organic Permeable Base Transistors—Reliable Large‐Scale Anodization for High Frequency Devices

AbstractOrganic permeable base transistors (OPBTs) have demonstrated impressive performance and potential in various applications, such as display driving circuits, light‐emitting transistors, and logic circuits requiring high‐frequency operation. However, large‐scale implementation is hindered by fabrication reliability and repeatability issues, a problem also common with other types of organic transistors, leading to reliance on exceptional “hero” devices. To address this challenge, an electrochemical anodization process is scaled up and optimized for OPBTs to produce consistent performance across an entire 15 cm × 15 cm wafer. By controlling the Al base oxidation, an 87% yield of functional devices and a median transconductance of d−3is achieved S, proving that the anodization process does not degrade the device performance. Additionally, anodization reduces leakage current to below d−9A, increasing the current gain to a median of 106, and decreases the oxide capacitance (Cox) without affecting the transconductance (gm), resulting in a driving‐voltage normalized unity‐gain cutoff frequency (fT/V) of up to 2.6 MHzV−1. The validity of the experimental results is confirmed through properly calibrated technology computer‐aided design (TCAD) simulations, which rely on DC and small‐signal AC analysis of OPBTs, based on the underlying physical equations.

Technology CAD for Microwaves: From Devices to Circuit Performance

Technology CAD for Microwaves: From Devices to Circuit Performance

Normally-Off Trench-Gated AlGaN/GaN Current Aperture Vertical Electron Transistor with Double Superjunction

This study proposes an AlGaN/GaN current aperture vertical electron transistor (CAVET) featuring a double superjunction (SJ) to enhance breakdown voltage (BV) and investigates its electrical characteristics via technology computer-aided design (TCAD) Silvaco Atlas simulation. An additional p-pillar was formed beneath the gate current blocking layer to create a lateral depletion region that provided a high off-state breakdown voltage. To address the tradeoff between the drain current and off-state breakdown voltage, the key design parameters were carefully optimized. The proposed device exhibited a higher off-state breakdown voltage (2933 V) than the device with a single SJ (2786 V), although the specific on-resistance of the proposed method (1.29 mΩ·cm−2) was slightly higher than that of the single SJ device (1.17 mΩ·cm−2). In addition, the reverse transfer capacitance was improved by 15.6% in the proposed device.

Efficient Neural Network-Based Compact Modeling for Novel Device Structures Using a Multi-Fidelity Model and Active Learning

Neural network (NN)-based compact modeling methodologies are gaining attention due to the challenges of device complexity, narrow model coverage, and SPICE simulation speed in advanced semiconductor technology nodes. As device complexity increases, the number of process and structural variables also increases, which significantly increases the amount of technology computer-aided design (TCAD) simulation data required for NN-based compact modeling. This study proposes a multi-fidelity model and active learning approach to predict global and local variations of nanosheet FETs (NSFETs) with less than 1.5% error, significantly reducing the number of required TCAD simulations by more than half compared with conventional modeling techniques. In addition, the simplified NN model with a smaller training dataset significantly reduces the SPICE simulation time.

Impact of deep and tail trap states on the electrical performance of double-gate ZnO thin film transistors

Abstract Traps in ZnO thin film transistors (TFTs) affect the electrical characteristics of the device. Traps originate primarily due to the disordered nature of the deposited semiconductor channel or are present at the ZnO and gate-dielectric interface. This work studies the effect of traps in double-gate ZnO TFTs using technology computer-aided design. The grain boundary and interface traps are assumed to be localized at the ZnO/SiO2 interface and are defined within the energy bandgap of ZnO using a double-exponential function. The traps are assumed to be of the acceptor type. The concentration of tail states is assumed to be 103 times more than in the deep state, while the characteristic temperature of deep state traps is assumed to be higher than the tail states. In common mode operation (i.e. both top and bottom gates are shorted), the tail states dominate the device characteristic compared with the deep state, while in independent mode (i.e. both gates are biased independently) the deep state traps affect the device characteristics more than the tail states.

Mitigating self-turn-on failures in scaled carrier stored trench IGBT: a focus on poly-Si resistivity

Abstract Scaled insulated gate bipolar transistors (IGBTs) show improvement in electrical performance, but their lower gate threshold voltage (V ge(th)) causes self-turn-on issues during high dV ce/dt or di c/dt switching conditions. In this study, we examine a carrier stored trench bipolar transistor (CSTBT) with a split-gate design to address the self-turn-on issue in scaled IGBTs. The split-gate configuration, which reduces Miller capacitance, helps to overcome self-turn-on failures of scaled split-gate CSTBT; however, the issue remains when considering the resistivity of poly-Si in the split-gates into account. To address this, we propose a selective-split-gate CSTBT design that resolves self-turn-on problems, even when poly-Si resistivity is considered. TCAD (Technology Computer Aided Design) simulations show that the proposed design is very effective in preventing self-turn-on and improves V ce(sat) by 24% compared to the scaled split-gate CSTBT.

Integrated Junction Barrier Schottky Diode and MOS-Channel Diode in SiC Planar MOSFETs for Optimization of Reverse Performances

A novel planar silicon carbide (SiC) MOSFET integrated with both MOS-channel diode (MCD) and junction barrier Schottky diode (JBS) on the same chip (MCD-JBSFET) is proposed and investigated through Technology Computer-Aided Design (TCAD) simulations in this paper. The proposed device features the lowest turn-on voltage and the best current conduction capability under the reverse-biased conditions, allowing it to achieve the same reverse conduction capability with fewer MCDs compared to conventional MOSFET with MCD structures (MCDFET). This reduction in the number of MCDs enables more channels to operate under forward-biased conditions, thereby improving power density. Compared to a conventional MOSFET integrated with JBS structure (JBSFET), the reverse current in the MCD-JBSFET flows through both the MCD and JBS, which suppresses the peak lattice temperature at Schottky contact and enhances the high-temperature robustness, especially under surge current conditions. In addition, the split-gate structure in the proposed structure optimizes the reverse capacitance and the figure of merit Ron,sp × Qg by factors of 0.65 and 2.15, respectively. Finally, the switching losses are reduced by 40.2%, indicating the suitability of MCD-JBSFET for high-frequency and high-current applications.

A Study on the Timing Sensitivity of the Transient Dose Rate Effect on Complementary Metal-Oxide-Semiconductor Image Sensor Readout Circuits.

Complementary Metal-Oxide-Semiconductor (CMOS) image sensors (CISs), known for their high integration, low cost, and superior performance, have found widespread applications in satellite and space exploration. However, the readout circuits of pixel arrays are vulnerable to functional failures in complex or intense radiation environments, particularly due to transient γ radiation. Using Technology Computer-Aided Design (TCAD) device simulations and Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulations, combined with a double-exponential current source fault injection method, this study investigates the transient dose rate effect (TDRE) on a typical readout circuit of CISs. It presents the variations in the photoelectric signal under different dose rates and at different occurrence moments of the TDRE. The results show that, under low dose rates, the CIS readout circuit can still perform data acquisition and digital processing, with the photoelectric signal exhibiting some sensitivity to the occurrence moment. At high dose rates, however, the photoelectric signal not only remains sensitive to the occurrence moment but also shows significant discreteness. Further analysis of the CIS readout circuit sequence suggests that the occurrence moment is a critical factor affecting the circuit's performance and should not be overlooked. These findings provide valuable insights and references for further research on the TDRE in circuits.

A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.

AlGan/GaN Based Dual-Cavity Structure for DNA Detection

In this study, the effect of sensitivity on the performance of dielectric modulated AlGaN/GaN is reported in to determine the device’s viability as a precise biosensor to detect both charged biomolecules based on the charge variations at the interface. This device utilizes the charge plasma effect, and the behavior is analyzed using variations in the threshold voltage and drain current for the improved performance. The device is simulated using the Sentaurus technology computer aided design (TCAD) simulator and specifically used to determine the biomolecules associated with DNA. The presence of HfAlO2 as the oxide provides unique insight for sensitivity improvement by reducing the leakage current with a high Ion/Ioff ratio. Moreover, the threshold voltage is shifted to positive for normally OFF behavior. The results imply a significant drain current (IDS) increase, up to 335 mA/mm. Finally, optimizing the device parameters increases sensitivity, making it an able candidate for future biosensing applications.

AlGaN/GaN High Electron Mobility Transistor (HEMT)-Based Dual-Metal Gate Architecture for Biosensing Applications

The electrical characteristics and sensitivity of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMTs) with dual metal single gate (DMSG) architecture are investigated and compared via Sentaurus technology computer aided design (TCAD) simulations with conventional single metal single gate (SMSG) devices. This technique reduces gate leakage and current collapse by using aluminium oxide as a high-k dielectric. Simulation results clearly reveal that DMSG devices exhibit superior performance with high drain current, high transconductance, and improved sensitivity compared to their SMSG counterpart. Moreover, precise sensing of biomolecules including zein, choline oxidase (ChOx), biotein, glucose, and urease has been investigated by adopting the DMSG structure. The band gap is ontinuity and peak electric field significantly improves the channel’s carrier confinement, leading to high sensitivity and making it feasible for the future biosensing applications.

Novel super stack passivation in AlGaN/GaN HEMT for power electronic applications

Abstract A super-stack passivation technique is proposed for an AlGaN/GaN HEMT in order to improve the breakdown voltage and cutoff frequency. The performance of the proposed technique is benchmarked against a conventional GaN HEMT. The analysis and investigation are carried out using Technology Computer-Aided Design (TCAD). The simulation results are validated with experimental data. It is observed that the breakdown voltage of the conventional and proposed devices is 356V and 449V, respectively. In contrast to the conventional device, the breakdown voltage of the proposed device is improved by 21%. This is the manifestation of the suppression of the electric field by the super-stack passivation technique in the proposed device. Furthermore, it is also observed that the Johnson’s figure of merit in the proposed GaN-HEMT is also improved.

Experimental-Modeling Framework for Identifying Defects Responsible for Reliability Issues in 2D FETs.

In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position. Once the trap energy distribution is extracted, it is used as input in transient TCAD simulations to reproduce the experimental hysteretic transfer characteristics. Our method is widely applicable to any 2D channel/gate stack combination. Here, it is demonstrated on FAB-integrated devices with AlOx/HfO2 gate oxide. A Gaussian-approximated defect band in the AlOx interlayer centered at a position of about 0.1 eV below the conduction band minimum of WS2 is obtained. Based on this energy position, it is concluded that aluminum interstitial and oxygen vacancies are the defects giving rise to the observed hysteresis. These defects are detrimental to the stability of the studied devices as they are easily accessible by channel carriers during on-state operation. A prominent hysteresis obtained during measurements is consistent with this conclusion.

Performance Analysis of JL-FinFET with Varied Non-Uniform Doping Concentrations, Fin Height and Fin Width using Device Simulator

With the growth of the MOSFET technology, the size of the transistor becomes smaller which can lead to Short-Channel Effects (SCEs). In order to address the SCEs, multi-gate transistor such as Fin Field-Effect Transistor (FinFET) has been invented. Meanwhile, it is found that the conventional transistor with junctions also has its drawbacks and limitations due to the decrease in the gate length. The SCEs can occur and affect the overall performance of the device with lower switching times and lower current density . In order to address these limitations, new structure of transistor without junction known as a junctionless (JL) transistor has been proposed. In this work, the impact of uniform versus non-uniform doping concentrations, fin height (Hfin) and fin width (Wfin) in JL-FinFET were investigated by using Technology Computer Aided Design (TCAD) Tools. It was found that non-uniform doping concentration of 4 x1018 cm-3 for the source/drain and of 4 x1017 cm-3 for the channel, together with Hfin of 20 nm and Wfin of 4 nm provide the best electrical performance of Ioff = 6.45 x10-17 A, Ion = 6.14 x10-6 A, Ion/Ioff = 9.52 x1010 and DIBL = 11 mV/V. The outcome of this research work can be used as a basis to understand JL-FinFET biosensors for medical applications and more complex JL structures.

Transient Current Analysis of GaN Neutron Detector Based on the SRIM and TCAD Methods

Utilizing Technology Computer Aided Design (TCAD) software, this study determines the optimal thickness and doping concentration for the intrinsic gallium nitride (GaN) layer in a p-i-n GaN diode to improve detection efficiency and reliability. The study examines energy loss and the transient current response induced by alpha and 3H particles within the GaN p-i-n diode. Additionally, TCAD elucidates the transient current behavior arising from electron-hole pair generation, utilizing the Stopping and Range of Ions in Matter SRIM-2013 linear energy transfer distribution as a guide. The simulations disclose that the tailing effect in the transient current response results from radiation-induced hole accumulation. Elevated applied bias results in increased transient current pulse amplitude, attributed to an extended depletion region that boosts carrier collection. These insights are expected to drive advancements in GaN-based neutron detector technology, essential for advancing nuclear and space science applications in the next generation.

AI‐assisted Field Plate Design of GaN HEMT Device

AbstractGaN High Electron Mobility Transistors (HEMTs) plays a vital role in high‐power and high‐frequency electronics. Meeting the demanding performance requirements of these devices without compromising reliability is a challenging endeavor. Field Plates are employed to redistribute the electric field, minimizing the risk of device failure, especially in high‐voltage operations. While machine learning is applied to GaN device design, its application to field plate structures, known for their geometric complexity, is limited. This study introduces a novel approach to streamlining the field plate design process. It transforms complex 2D field plate structures into a concise feature space, reducing data requirements. A machine learning‐assisted design framework is proposed to optimize field plate structures and perform inverse design. This approach is not exclusive to the design of GaN HEMTs and can be extended to various semiconductor devices with field plate structures. The framework combines technology computer‐aided design (TCAD), machine learning, and optimization, streamlining the design process.

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.

TCAD‐enabled machine learning framework for DC and RF performance evaluation of InGaAs sub‐channel DG‐HEMTs

AbstractThis research presents a machine learning (ML)‐based model that determines the DC and RF characteristics of InGaAs sub‐channel double gate high electron mobility transistors (DG‐HEMTs) to optimize the device structure. We employ technology computer‐aided design (TCAD) simulations to analyze the DC and RF performance of InGaAs sub‐channel DG‐HEMTs, generating a range of datasets by varying the material composition, layer width, and thickness of different layers in the device structure. We then train and optimize support vector regression (SVR) models using 5‐fold cross‐validation, varying the kernel function and degree parameters, and achieve better performance with the radial basis function (RBF) kernel. The simulated results indicate that the ML model predicts physical parameters more effectively than experimental analysis, offering a compact modeling solution that requires fewer computing resources than traditional methods.