Technology Computer-aided Design Research Articles

Comprehensive Design and Analysis of Thin Film Sb2S3/CIGS Tandem Solar Cell: TCAD Simulation Approach

Abstract This research presents a design and analysis of a tandem solar cell, combining thin film wide bandgap Sb2S3 (1.72 eV) and narrow bandgap CIGS (1.15 eV) for the top and bottom sub-cells, respectively. The integration of all thin film layers enhances flexibility, rendering the tandem solar cell suitable for applications such as wearable electronics. To optimize the power conversion efficiency (PCE) of the tandem solar device, advanced technology computer-aided design (TCAD) simulation tools are employed to estimate loss mechanisms and fine-tune parameters for each layer. An experimentally validated optoelectronic model is introduced, calibrated and validated against fabricated reference solar cells for the individual top and bottom cells. The calibrated model is then utilized to propose optimization routines for the Sb2S3/CIGS tandem solar cell. The initial tandem cell exhibits a JSC of 15.72 mA/cm2 and a PCE of 15.36%. The efficiency drop in the tandem configuration is identified primarily in the top cell. A systematic optimization process for the top cell is initiated, exploring various configurations, including HTL-free and ETL-free setups. Moreover, an np homojunction structure for the top cell is proposed. Optimization routines are applied that involve determining optimal thickness and doping concentration of the n-layer, investigating the effect of p-layer doping concentration, and exploring the influence of the work function of the front contact. As a result, the tandem cell efficiency is significantly improved to 23.33% at the current matching point (CMP), with a JSC of 17.15 mA/cm2. The findings contribute to the advancement of thin-film tandem solar cell technology, showcasing its potential for efficient and flexible photovoltaic applications.

High-Efficiency Vertical-Chip Micro-Light-Emitting Diodes via p-GaN Optimization and Surface Passivation

Micro-LEDs have found widespread applications in modular large-screen TVs, automotive displays, and high-resolution-density augmented reality glasses. However, these micron-sized LEDs experience a significant efficiency reduction due to the defects originating from the dry etching process. By controlling the current distribution via engineering the electrode size, electrons will be less concentrated in the defect region. In this work, we propose a blue InGaN/GaN compound parabolic concentrator micro-LED with a metallic sidewall to boost efficiency by combining both an optical dipole cloud model and electrical TCAD (Technology Computer-Aided Design) model. By merely modifying the p-GaN contact size, the external quantum efficiency (EQE) can be improved by 15.6%. By further optimizing the passivation layer thickness, the EQE can be boosted by 52.1%, which helps enhance the display brightness or lower power consumption.

Study of drain-induced channel effects in vertical GaN junction field-effect transistors

A normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) is demonstrated in this work. The device shows an on/off current ratio of 3.6 × 1010, a threshold voltage (V TH) of 1.64 V, and a specific on-resistance (R ON,SP) of 1.87 mΩ·cm2. Drain-induced channel effects were proposed to explain the change in the gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by effects. A technological computer-aided design was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of novel structures. The characteristics at different temperatures demonstrated the stability of threshold voltage and specific on-resistance, thus indicating the great potential of applications in switching power circuits of vertical GaN JFETs.

Prediction of electrical properties of GAAFET based on integrated learning model

As device feature sizes continue to decrease and fin field effect transistors reach their physical limits, gate all around field effect transistors (GAAFETs) have emerged with larger gate control areas and stackable characteristics for better suppression of second-order effects such as short-channel effects due to their gate encircling characteristics. Traditional methods for studying the electrical characteristics of devices are mostly based on the technology computer-aided design. Still, it is not conducive to developing new devices due to its time-consuming and inefficient drawbacks. Deep learning (DL) and machine learning (ML) have been well-used in recent years in many fields. In this paper, we propose an integrated learning model that integrates the advantages of DL and ML to solve many problems in traditional methods. This integrated learning model predicts the direct current characteristics, capacitance characteristics, and electrical parameters of GAAFET better than those predicted by DL or ML methods alone, with a linear regression factor (R 2) greater than 0.99 and very small root mean square error. The proposed integrated learning model achieves fast and accurate prediction of GAAFET electrical characteristics, which provides a new idea for device and circuit simulation and characteristics prediction in microelectronics.

An investigation into the thermal surface contact resistance, fin width and temperature on negative bias temperature instability during self-heating

This work investigates the impacts of the thermal surface contact resistance (SR), fin width and temperature on the negative bias temperature instability (NBTI) during self-heating based on 14 nm p-FinFET through technology computer-aided design (TCAD) tool. In order to promote the accuracy of simulation, the experimental data are used to calibrate the TCAD results. The simulation results reveal that as SR increases, the lattice temperature rises by 20.07 %, which leads to a 15.84 % decrease of the carrier mobility and finally a reduction of the saturation current by 5.07 %. Moreover, as WFin decreases from 8 nm to 2 nm, the device threshold voltage increases by 15.41 %, resulting in that the saturation current reduces by 19.06 %. Besides, with an increase of the ambient temperature from 300 K to 500 K, the lattice temperature and trapped charge rise by 60.48 % and 12.53 %, respectively, which eventually leads to an 18.13 % decrease of the saturation current.

Impact of the recessed gate depth on the GaN metal-oxide-semiconductor high electron mobility transistor performances: New insights on mobility extraction

This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. IDS = f(VGS) and IDS = f(VDS) measurements are conducted at 25 and 150 °C, respectively, in forward and blocking modes. The gate recessed depth (50, 150, and 350 nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom (μbot) and the entire sidewall region mobility (μT), without distinction from the corner. The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner (μcorner) and sidewall (μSW) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one (μcorner < μSW) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance (RON). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain–source leakage current in reason of a lower gate electrostatic control. Technology Computer Aided Design (TCAD) simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology.

Analysis on performances of ultra-thin vertical MOSFET depending on position of gate–drain misalignment

In advanced MOSFET design, a vertical-channel structure provides the advantages of a smaller footprint of the transistor cell and stronger immunity against short-channel effects by introducing higher freedom in determining the channel length. For these reasons, vertical devices are still predicted to be an upcoming solution in the most recent technology roadmap. However, due to the cell-to-cell or wafer-to-wafer processing deviation that inevitably exists, it can be quite challenging to locate the gate edges at the exact positions that maximize the device performance. In this work, a series of technology computer-aided design (TCAD) device simulations have been carried out to investigate the effects of gate underlap and overlap structures on the device performance of vertical-channel MOSFETs. The device characterizations were conducted from the aspects of both DC and HF operations for higher completeness of this work, since both are not usually optimized at the same time under the same structural and processing conditions. Under the underlap condition, slight degradation in the on-state current (I on) drivability was observed. On the other hand, a noticeable off-state current (I off) increase was witnessed under the underlap conduction. It is explicitly demonstrated that excessive gate underlap results in non-ideal effects, including degradation of the subthreshold swing (S), worsening of drain-induced barrier lowering, and lowering of the maximum transconductance (g m,Max). In the HF analyses, although f T and f max remained high under overlap and gate–drain alignment conditions, it was observed that both were likely to deteriorate under underlap conditions. As a result, a processing margin in the anisotropic etching of the gate can be obtained for the optimization of the DC and HF performance of vertical-channel MOSFETs, paving the way for a wide variety of low-power and high-speed analog and digital applications.

A design methodology for highly reliable operation for 2T0C DRAM application based on IGZO CAA FeFETs

Abstract In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical Channel-All-Around (CAA) structure are investigated by technology computer-aided design (TCAD) simulation. The simulated IDS~VGS curves of IGZO FeFET exists a large on-off ratio of 107 and memory window, proving that ferroelectric hafnium oxide is satisfied for 2T0C transistor design. To solve the potential current sharing problem of 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of ferroelectric hafnium oxide. This solution shows the remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of IGZO-based FeFET on 2T0C DRAM memory cell, but also providing array design guideline for highly reliable 2T0C memory applications.

Damage Effects and Mechanisms of High-Power Microwaves on Double Heterojunction GaN HEMT

In this paper, simulation modeling was carried out using Sentaurus Technology Computer-Aided Design. Two types of high electron mobility transistors (HEMT), an AlGaN/GaN/AlGaN double heterojunction and AlGaN/GaN single heterojunction, were designed and compared. The breakdown characteristics and damage mechanisms of the two devices under the injection of high-power microwaves (HPM) were studied. The variation in current density and peak temperature inside the device was analyzed. The effect of Al components at different layers of the device on the breakdown of HEMTs is discussed. The effect and law of the power damage threshold versus pulse width when the device was subjected to HPM signals was verified. It was shown that the GaN HEMT was prone to thermal breakdown below the gate, near the carrier channels. A moderate increase in the Al component can effectively increased the breakdown voltage of the device. Compared with the single heterojunction, the double heterojunction HEMT devices were more sensitive to Al components. The high domain-limiting characteristics effectively inhibited the overflow of channel electrons into the buffer layer, which in turn regulated the current density inside the device and improved the temperature distribution. The leakage current was reduced and the device switching characteristics and breakdown voltage were improved. Moreover, the double heterojunction device had little effect on HPM power damage and high damage resistance. Therefore, a theoretical foundation is proposed in this paper, indicating that double heterojunction devices are more stable compared to single heterojunction devices and are more suitable for applications in aviation equipment operating in high-frequency and high-voltage environments. In addition, double heterojunction GaN devices have higher radiation resistance than SiC devices of the same generation.

Strong Immunity to Drain-Induced Barrier Lowering in ALD-Grown Preferentially Oriented Indium Gallium Oxide Transistors.

Drain-induced barrier lowering (DIBL) is one of the most critical obstacles degrading the reliability of integrated circuits based on miniaturized transistors. Here, the effect of a crystallographic structure change in InGaO [indium gallium oxide (IGO)] thin-films on the DIBL was investigated. Preferentially oriented IGO (po-IGO) thin-film transistors (TFTs) have outstanding device performances with a field-effect mobility of 81.9 ± 1.3 cm2/(V s), a threshold voltage (VTH) of 0.07 ± 0.03 V, a subthreshold swing of 127 ± 2.0 mV/dec, and a current modulation ratio of (2.9 ± 0.2) × 1011. They also exhibit highly reliable electrical characteristics with a negligible VTH shift of +0.09 (-0.14) V under +2 (-2) MV/cm and 60 °C for 3600 s. More importantly, they reveal strong immunity to the DIBL of 17.5 ± 1.2 mV/V, while random polycrystalline In2O3 (rp-In2O3) and IGO (rp-IGO) TFTs show DIBL values of 197 ± 5.3 and 46.4 ± 1.2 mV/V, respectively. This is quite interesting because the rp- and po-IGO thin-films have the same cation composition ratio (In/Ga = 8:2). Given that the lateral diffusion of oxygen vacancies from the source/drain junction to the channel region via grain boundaries can reduce the effective length (Leff) of the oxide channel, this improved immunity could be attributed to suppressed lateral diffusion by preferential growth. In practice, the po-IGO TFTs have a longer Leff than the rp-In2O3 and -IGO TFTs even with the same patterned length. The effect of the crystallographic-structure-dependent Leff variation on the DIBL was corroborated by technological computer-aided design simulation. This work suggests that the atomic-layer-deposited po-IGO thin-film can be a promising candidate for next-generation electronic devices composed of the miniaturized oxide transistors.

Modeling and Bulk Characterization of 4HSIC Radiation Detector in Sentaurus TCAD Simulation Environment

This paper gives an insight into the need for radiation detection and the most commonly flexible and efficient radiation detector. It also examines bulk characteristics of 4H-SiC semiconductor radiation detector with Ni and Ti as metals for the contact. Bulk characterization of the device, including: doping concentration, electrons and holes behaviors, space charge and current densities were carried out. The modeling is conducted using Sentaurus Technology Computer Aided Design (TCAD) to examine charge transport in bulk 4HSiC material. Data obtained were further analyzed through Sentaurus visual, sentaurus Techplot and Excel to clearly determine the characteristics of the device. It is observed that when the semiconductor and metal are in contact, the Fermi-level is established where the doping concentration varied with either magnitude of the doping concentration or nature of the dopant. Similarly, Schottky and ohmic contacts and temperature effect were observed from the device characteristics which demonstrate that, the detector can withstand a temperature from the range of 100K to 700K in no fluctuating state.

Enhanced Breakdown Voltage of AlGaN/GaN MISHEMT using GaN Buffer with Carbon-Doping on Silicon for Power Device

In recent years, Gallium Nitride (GaN)-based metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) have attracted interest in high-power and high-frequency applications. The breakdown mechanism in E-mode GaN MISHEMTs with carbon doping in the GaN buffer grown on a Silicon (Si) substrate (Sub) was investigated using technology computer-aided design simulations. Results showed that GaN MISHEMTs without Si Sub had a breakdown voltage (BV) of 600 V. However, after adding Si Sub to the GaN buffer layer, the electric field (EF) increased, creating a vertical breakdown through the total buffer thickness, therefore, BV was reduced to around 240 V. On the other hand, BV is increased to approximately >1100 V, and the Electric field is reduced after employing a carbon deep acceptor with the proper doping concentration in this device. The GaN MISHEMTs with Si Sub is presented as threshold voltage +1.5 V with transconductance of 700 mS/mm, which is an excellent result compared to GaN MISHEMTs without Si Sub. Eventually, the study device depicted higher BV performance compared to other C-doped GaN HEMT devices. This suggests that the designed GaN MISHEMTs device could effectively be used in power semiconductor devices with optimum performance.

GaN-HEMT Performance Enhancement

In this work, a simulation analysis and calibration are carried out to improve the performance of AlGaN/GaN- MOSHEMTs (Metal-Oxide Semiconductor High Electron Mobility Transistors). The effect of the AlGaN layer thickness, gate length, Al mole fraction, and the interface traps on the electrical performance of the device has been presented. Device simulations have been done using Sentaurus technology computer-aided design (TCAD). The simulations and analysis show better drain current, transconductance, and cut-off frequency performance. The maximum cut-off frequency shown by the proposed HEMT device is 45.7 GHz at 100-nm gate length. Good transcoductance has been obtained by scaling down the gate length of the device, which is ascribed to the present two-dimensional electron gas (2DEG) density that supports upgrading the output current. Higher drain current is achieved without using acceptor-like traps in the Al2O3/AlGaN interface. Results show that the Al2O3/AlGaN/GaN-based MOSHEMT is a promising device for high-frequency and power electronic applications.

Characteristics of β-(AlxGa1−x)2O3/Ga2O3 dual-metal gate modulation-doped field-effect transistors simulated by TCAD

β-(AlxGa1−x)2O3/Ga2O3 modulation-doped field-effect transistors (MODFETs) with a dual-metal gate (DMG) architecture are designed, and the electrical characteristics of the DMG device are investigated in comparison with the single-metal gate (SMG) device by the Technology Computer-Aided Design (TCAD) simulation. The results demonstrate that the DMG MODFETs possess a superior transconductance (gm), current gain cut-off frequency (fT), and power gain cut-off frequency (fMAX) than those of SMG transistors, which is attributed to the regulated channel electric field by a DMG structure. With a gate length of 0.1 μm, the peak values of fT/fMAX of the designed DMG MODFET are obtained as 48.6/50.6 GHz, respectively. Moreover, a comprehensive thermal analysis is conducted between the SMG and DMG devices under steady-state and transient conditions. The DMG MODFET exhibits a lower maximum temperature than the SMG counterpart due to the reduced channel electric field, each subjected to the same power dissipation. This finding underscores the potential of the β-(AlxGa1−x)2O3/Ga2O3 MODFET with the DMG architecture as a promising approach for high-power radio frequency operations.

Optimization of laser annealing parameters based on bayesian reinforcement learning

AbstractDeveloping new semiconductor processes consumes tremendous time and cost. Therefore, we applied Bayesian reinforcement learning (BRL) with the assistance of technology computer-aided design (TCAD). The fixed or variable prior BRL is tested where the TCAD prior is fixed or is changed by the experimental sampling and decays during the entire RL procedure. The sheet resistance (Rs) of the samples treated by laser annealing is the optimization target. In both cases, the experimentally sampled data points are added to the training dataset to enhance the RL agent. The model-based experimental agent and a model-free TCAD Q-Table are used in this study. The results of BRL proved that it can achieve lower Rs minimum values and variances at different hyperparameter settings. Besides, two action types, i.e., point to state and increment of levels, are proven to have similar results, which implies the method used in this study is insensitive to the different action types.

The stability analysis of In–Ga–ZnO thin film transistors with polyimide substrates based on Maxwell–Wagner effect

Flexible organic light-emitting diode display devices fabricated on polyimide (PI) substrates have more obvious residual image problems due to the abnormal threshold-voltage (Vth) shifts of a thin film transistor (TFT). In this paper, the Vth shift of TFT fabricated on a PI substrate was analyzed. We explained the worse bias stability and worse recovery of TFT with a PI substrate compared with TFT with a glass substrate, by an interlayer charging effect (Maxwell–Wagner effect) and a technology computer-aided design (Silvaco). When bias stress was applied for a long time, the interface between the PI substrate and the buffer layer will have a charging effect under the action of an electric field, and the charging charge will react on the channel and hinder the formation of the channel. We found that there are differences in the scale of charge under different voltage stress conditions, and this will result in different Vth shifts of driving TFTs for displays units.

Non-equilibrium thermal transport study in steady state GaN MISHEMT channel layer based on electron Monte Carlo and phonon BTE

An electro-thermal coupling simulator for GaN devices based on electron Monte Carlo (e-MC) simulations is established. Taking GaN Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) as example, the non-equilibrium thermal transport processes of self-heating effect in the channel layer are studied. This simulator is mainly coupled by e-MC and the phonon Boltzmann transport equation (pBTE), physical property parameters and electric field parameters are provided by first-principles and Technology Computer Aided Design (TCAD), respectively. We first verify the e-MC program by calculating the electron transport properties of GaN materials, verify the feasibility of the established GaN MISHEMT model by using TCAD and obtained its operating characteristics. Further, the simulator is used to evaluate the non-equilibrium processes inside the channel layer in detail, the results show that there is significant consistency in the peak positions of electric field strength, heat generation and diffusion temperature, the diffusion temperature peak occurs at the secondary peak of heat generation. The frequency distribution of phonon emission under different drain-source bias voltages is revealed by phonon emission spectrum analysis. The strength of the non-equilibrium effect is measured by effective temperature. Increasing the drain-source bias voltage will significantly increase the peak temperature of hotspot and further enhance the non-equilibrium effect. Our study reports an efficient scheme for electro-thermal simulations of GaN MISHEMT, which provides insights for thermal management of GaN-based transistor devices.

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.

Investigation on electrical parameters between single and double material gate nanoribbon FETs including trap distributions

The presence of multiple interface of gate-oxide and semiconductor in Nano-ribbon FET (NR-FET) causes several defects and leads to the degraded electrical parameters. In this regard, the electrical parameters in the existence of interface trap charges (ITCs) for single material gate (SMG) and double material gate (DMG) NR-FETs are extracted using Technology Computer Aided Design (TCAD) simulator. The effect of Uniform/Gaussian ITCs at the oxide and semiconductor interface on drain current, electrostatic potential, ON current, OFF current, and threshold voltage are reported for these devices. The RF/analog performance like transconductance (gm), gate capacitance (Cgg), and cut-off frequency (fc) are reported for these structures in presence of non-ideal trap distributions. Moreover, the linearity parameters like higher order harmonics in gm (gm2 and gm3), voltage intercept points (VIP2 and VIP3), input intercept power (IIP3), and intermodulation distortion (IMD3) are highlighted for these structures. It is seen that DC, RF/analog, and linearity performance of both the NRFETs are significantly affected by Uniform and Gaussian distribution of ITCs. However, the electrical parameters in DMG NRFET is more immune to ITCs than SMG NRFET. Moreover, both the devices have ON state current in the order of 10−3 A, fc of order THz, and improved linearity behaviour in the presence of ITCs, which indicates sustainability of these devices including ITCs.