The dependence of electrical characteristics of a BCD (bipolar-CMOS-DMOS) technology highside nLDMOS (n-channel laterally diffused metal oxide semiconductor) on its process and structural parameters is investigated, and an improved 0.18-μm BCD 5 V gate and 80 V drain operatingvoltage high-side nLDMOS is proposed for high breakdown voltage and low specific on-resistance applications. The nLDMOS was designed to meet the drain breakdown voltage of BVDSS = 100 V at the gate voltage of VGS = 0 V and the specific on-resistance of Rsp = 115 [mΩ-mm ] at VGS = 5 V and the drain voltage of VDS = 0.1 V, using TCAD (technology computer-aided design) simulation. The figure-of-merit, BVDSS/Rsp = 87 [V /(mΩ-mm)], of the integrated nLDMOS is better than the figures-of-merit of other BCD nLDMOS published recently. Design guidelines for the high BVDSS and low Rsp nLDMOS are provided. The epitaxial layer thickness, the deep N-well (or high-voltage N-well) ion implant (I/I) dose / energy, the deep N-well drive-in time, the window length of an additional N-drift ion implant and structural parameters are important in designing the improved nLDMOS. The trade-off between BVDSS and Rsp of the improved nLDMOS is no longer valid in a range of the N-drift ion implant window length and deep N-well drive-in time. To increase confidence of simulation results on 0.18-μm BCD 80 V nLDMOS, we calibrated some TCAD model parameters, using measured characteristics of 0.18-μm BCD 40 V nLDMOS.