Interconnection Techniques Research Articles

Optimization of Micro-Pillars Electroplating Bonding Processes and Additives

Abstract With the increasing interconnect density of electronic components, copper-copper direct bonding technology has garnered increasing attention from researchers. The electroplating bonding method is an efficient copper pillar interconnection technique that can be implemented at room temperature and atmospheric pressure. COMSOL simulation results show that under convective conditions, the plating layer primarily deposits on the convection exit side of the copper plate. Under weak convection and low current density, the plating exhibits deposition characteristics that conform to the substrate surface. As convection intensity increases, preferential deposition begins to occur, although the overall deposition rate decreases. At this point, when the current density is increased, the deposition pattern predominantly shows preferential deposition; however, excessively high current density can lead to copper deposition in non-bonding areas. Orthogonal experimental results indicate that, within the accelerator bis(3-sulfopropyl) disulfide (SPS) – inhibitor polyethylene glycol (PEG) – leveling agent Jenner Green B (JGB) – chloride ion (Cl-) system, the influence of the four additives on bonding strength follows this order: JGB > Cl- > SPS > PEG. The optimal formulation derived from the orthogonal experiments is SPS 2 ppm, PEG (8000) 150 ppm, JGB 5 ppm, and Cl- 30 ppm, which results in a shear strength of 123.2 MPa. These findings suggest that high-strength copper pillar interconnections can be achieved by adjusting physical parameters such as the electric field, flow field, and additive concentrations.

3D integration of pixel readout chips using Through-Silicon-Vias

Particle tracking and imaging detectors are becoming increasingly complex, driven by demands for densely integrated functionality and maximal sensitive area. These challenging requirements can be met using 3D interconnect techniques widely used in industry. In this paper, we present the results of an evaluation of the 3D Through-Silicon-Via (TSV) technology, using the Timepix4 integrated circuit as a test-vehicle. We will present the concepts for 3D integration and test results from TSV-processed chips bonded to custom-designed circuit boards conceived as proofs-of-principle for future detector modules.

Performance Analysis of Interconnection and Differential Power Processing Techniques under Partial Shading Conditions

Partial shading conditions can cause low output power, hotspots, and a reduced lifespan in photovoltaic arrays. Interconnection (IC) and differential power processing (DPP) can be used to mitigate these effects. When individually applied to an array, these techniques can significantly increase the generated power. A few authors studied the combined use of these schemes under specific conditions such as large-scale arrays or a complex combination of several techniques, making it difficult to identify the individual contribution of each technique. Here, we aimed to determine whether the combined use of a switching-inductor DPP circuit and a total-cross-tied interconnection scheme presents better performance than each standalone technique, using a small-scale photovoltaic array. An array was tested using IC, DPP, and a combination of both techniques, and the array was subjected to 13 shading patterns and two irradiance levels. The performance in each case was assessed using maximum output power, performance ratio, mismatch power loss, and power enhancement indicators. The results showed that a standalone differential power processing circuit presents better performance than when it is combined with an interconnection. The DPP showed performance ratio values of up to 97%, mismatch power losses lower than 36.9%, and a power enhancement of up to 95.9%. The standalone interconnection shows the worst performance among the three techniques.

Assembly of Printed Interconnects for Immobilized Protein Microfluidic Assays

Microfluidics has attracted significant attention for biological applications, particularly for high-throughput screening and multiplexing. However, conventional interconnect techniques are limited in their ability to fabricate the hundreds or thousands of microfluidic interconnects needed to process multiple samples for high-throughput microfluidics. To address this challenge, coaxial printing was invented to enable rapid, customizable, and scalable microfluidic interconnects. This paper focuses on the assembly process of coaxial printed interconnects for immobilized protein microfluidic assays. We demonstrate the immobilization of protein into a 1 x 1 microwell microfluidic unit with printed connectors to showcase the process.

Gradient-descent noise whitening techniques for short-reach IM-DD optical interconnects with severe bandwidth limitation.

Bandwidth limitation in optoelectrical components and the chromatic dispersion-induced power fading phenomenon cause severe inter-symbol interference (ISI) in high-speed intensity modulation and direct detection (IM-DD) optical interconnects. While the equalizer implemented in the receiver's digital signal processing procedure can mitigate ISI, it also inevitably enhances the noise located in the decayed frequency region, known as equalization-enhanced colored noise (EECN). Additionally, the nonlinear impairments of the modulator and photodetector also deteriorate the performance of the IM-DD system, especially for high-order modulation formats. In this work, we propose a gradient-descent noise whitening (GD-NW) algorithm to address EECN and extend it by introducing nonlinear kernels to simultaneously mitigate EECN and nonlinear impairments. The proposed algorithms are compared with conventional counterparts in terms of the achievable baud rate and the receiver optical power sensitivity. As a proof-of-concept experiment, we validate the principles of the proposed algorithms by successfully transmitting 360-GBd on-off-keying (OOK) and 180-GBd 4-level pulse-amplitude-modulation (PAM-4) signals in the back-to-back case under a 62-GHz brick-wall bandwidth limitation. 280-GBd OOK and 150-GBd PAM-4 transmissions are also demonstrated over 1-km standard single-mode fiber with a bit error rate below 7% hard-decision forward error correction aided by the proposed approach.

Conditional spatial transition reduction data encoding technique for VLSI interconnects

In this paper the DSM (Deep sub micron) and lower node technologies device dimensions are reduced. Compared to logic functional blocks interconnects dynamic power consumption plays most precarious factor. The most effective way to save the dynamic power in wires is to reduce the number of transitions by using the data encoder. In this paper we proposed a inverse based algorithm with mathematical proof and simple architecture. it is having the different options lower bit inversion, upper bit inversion, all bit inversions and no bit inversion, the data selection based on the which option saves the more power. It is having the simple and compact architecture and it offers less delay compared to related methods.

RF Interconnection Design of Bump Bonding with a Dislocation Package Structure towards Electro-Optic Modulation Applications

Bonding technology can be an important component of packaging for photonic chips, such as electro-optic (EO) modulators and other active function devices. In general, an EO modulator chip can achieve a broader 3 dB EO bandwidth than its packaging device, as the packaging design and structure can technically limit modulation performance. Recently, bump bonding has been shown to be a good candidate for the EO interconnection technique, which has a higher transmission bandwidth than wire bonding. In this article, we propose a design for radio frequency (RF) interconnection of bump bonding with a dislocation packaging (BBDP) structure. Through simulation calculations and analysis, the proposed BBDP structure shows a 3 dB transmission bandwidth of approximately 145 GHz, which is 52.6% better than one using optimized wire-bonding structures (95 GHz). The proposed packaging structure presents an important alternative method for ultrahigh speed optical modulation applications.

Package Board Co-Simulation Using Equivalent Circuit Modeling Method for High-Speed System

This research paper focuses on the challenges of system-level simulations for high-speed data transfer and the importance of modeling methodology in achieving accurate results. The simulating of PCB alone without considering the package model is not enough. Instead, to ensure optimal system performance, simulating the packages and PCBs together is essential. When simulating the high-speed parallel bus at the PCB level, it's crucial to consider the package model. If the package model is missing, achieving successful results can be challenging. In this paper, a method is proposed for developing a package model that is specific to the nets required for simulation purposes. The paper explores the challenge of simulating high-speed interfaces with a DDRx example that includes an RLC package model. An interconnect model technique is developed to apply the package RLC model through the equivalent circuit modeling method for the high-speed DDRx test board. This solution aims to simplify the co-design process by using simulation and verifying the model with the assistance of an eye diagram of the data bus. The proposed package model reduces jitter in co-simulation and ensures timing compliance for high-speed interfaces.

Substrate-Integrated Hybrid Metallo-Dielectric Waveguide Architecture for Millimeter-Wave and Terahertz Applications

In millimeter-wave (mmW) and terahertz (THz) applications, the transmission behavior along circuit structures and components, such as radiation and leakage losses, is critical for their overall performances. It is imperative to develop low-loss interconnect and transmission techniques that should be used for the construction of building circuit blocks and elements. In this work, a hybrid metallo-dielectric (MD) waveguide architecture is proposed and studied for the first time. The scheme is made of mixed substrate-integrated dielectric waveguide (SIDW) and substrate-integrated nonradiative dielectric (SINRD) waveguide, which are deployed for the design of specific building parts in consideration of respective transmission properties of the two waveguides. A back-to-back WR3-band prototype based on this hybrid scheme is investigated theoretically and validated experimentally. The hybrid MD waveguide architecture with SINRD is found to outperform the hybrid MD waveguide architecture with substrate-integrated waveguide (SIW) in terms of transmission performance and manufacturing complexity because of the advantageous features of metallized-via-free structure. The presented hybrid MD waveguide architecture shows its potential for developing low-loss highly integrated mmW and THz circuits and systems.

Development of repairing technique for interconnection of silicon photovoltaic modules using an induction heating system

One of the origins for the degradations of the performance in Si photovoltaic (PV) modules is the corrosions of the front-side metallization, joints of solder and electrodes, solder and interconnection ribbons, thus increasing the series resistance after long-term exposure. This work proposes a reliable method to repair the failures of solder interconnections by utilizing the local induction heating system. The method will perform without removing the PV modules from the outdoor installation locations leading to time-saving and low maintenance costs. It reveals that the heating time on the failures of the solder joint and solder interconnection in the Si PV module plays a vital role in decreasing the series resistance and recovering the PV performance. The optimized heating conditions were a time of 2.0 s, a 10% output power of 3.5 kW, and a frequency of 900 kHz. The proposed method is effective and yields the recovery of the conversion efficiency of the Si solar cell module, as also confirmed by electroluminescence imaging.

Novel SMD Component and Module Interconnection and Encapsulation Technique for Textile Substrates Using 3D Printed Polymer Materials.

Nowadays, a range of sensors and actuators can be realized directly in the structure of textile substrates using metal-plated yarns, metal-filament yarns, or functionalized yarns with nanomaterials, such as nanowires, nanoparticles, or carbon materials. However, the evaluation or control circuits still depend upon the use of semiconductor components or integrated circuits, which cannot be currently implemented directly into the textiles or substituted by functionalized yarns. This study is focused on a novel thermo-compression interconnection technique intended for the realization of the electrical interconnection of SMD components or modules with textile substrates and their encapsulation in one single production step using commonly widespread cost-effective devices, such as 3D printers and heat-press machines, intended for textile applications. The realized specimens are characterized by low resistance (median 21 mΩ), linear voltage-current characteristics, and fluid-resistant encapsulation. The contact area is comprehensively analyzed and compared with the theoretical Holm's model.

224-Gbit/S 4-PAM Operation of Compact DC Block Circuit Integrated Hi-FIT AXEL Transmitter With Low Power Consumption

We previously developed a semiconductor optical amplifier (SOA) assisted extended reach electroabsorption modulator integrated distributed feedback (EADFB) laser (AXEL) to increase the optical modulation output power and a high-frequency integrated design based on the flip-chip interconnection technique (Hi-FIT) to obtain a high modulation bandwidth. We achieved a high-output power 224-Gbit/s 4-level pulse-amplitude-modulation (4-PAM) operation of a Hi-FIT AXEL module. In this paper, we developed a compact DC block circuit integrated into Hi-FIT AXEL module to decrease chip-power consumption without increasing the sub-assembly size and degrading the modulation bandwidth. We designed a Hi-FIT AXEL sub-assembly, that include a flip-chip interconnection board with a DC block circuit that affects the modulation bandwidth. We achieved a 3-dB bandwidth of up to 64 GHz for this designed sub-assembly. The fabricated Hi-FIT AXEL module has a 3-dB bandwidth of more than 62 GHz and a flat frequency response up to 50 GHz. For the 224-Gbit/s 4-PAM operation, the fabricated Hi-FIT AXEL module has a chip-out average output power of +10.0 dBm with a transmitter eye-closure quaternary (TECQ) of 1.9 dB. The integrated compact DC block circuit can reduce chip power consumption by up to 17%.

17.1: SRAM‐based LED CMOS driver circuit for a 512x512 GaN microdisplay

GaN microLED technology has the potential to offer displays with high brightness, bandwidth, and long lifetime with a very low energy consumption. Moreover, GaN‐on‐Si hybrid interconnection technology allows the development of displays with a very high pixel density integration. In this work we present an in‐pixel driving circuit designed in a 0.18µm CMOS technology to be integrated on a 512x512 microLED array by using the KlettWelding hybrid interconnection technique forming a microLED display of 1411 ppi with 10kfps working speed. The pixel driver is able to achieve switching times of 1MHz and can be operated at high bias currents of 120µA. The individual driver consists of 4 SRAMs that apply a weighted current and allows to avoid the current stability problems associated to CMOS backplanes in hybridly interconnected displays.

Solid-state 360° optical beamforming for reconfigurable multicast optical wireless communications.

Optical wireless communication is an attractive technique for data center interconnects due to its low latency line-of-sight connectivity. Multicast, on the other hand, is an important data center network function that can improve traffic throughput, reduce latency, and make efficient use of network resources. To enable reconfigurable multicast in data center optical wireless networks, we propose a novel 360° optical beamforming scheme based on the principle of superposition of orbital angular momentum modes, emitting beams from the source rack pointing towards any combination of other racks so that connections are established between the source and multiple destination racks. We experimentally demonstrate the scheme using solid state devices for a scenario where racks are arranged in a hexagonal formation in which a source rack can connect with any number of adjacent racks simultaneously, with each link transmitting 70 Gb/s on-off-keying modulations at bit error rates of <10-6 at 1.5-m and 2.0-m link distances.

Development of a large-area, light-weight module using the MALTA monolithic pixel detector

The MALTA pixel chip is a 2 cm × 2 cm large monolithic pixel detector developed in the Tower 180 nm imaging process. The chip contains four CMOS transceiver blocks at its sides which allow chip-to-chip data transfer. The power pads are located mainly at the side edges on the chip which allows for chip-to-chip power transmission. The MALTA chip has been used to study module assembly using different interconnection techniques to transmit data and power from chip to chip and to minimise the overall material budget. Several 2-chip and 4-chip modules have been assembled using standard wire bonding, ACF (Anisotropic Conductive Films) and laser reflow interconnection techniques. These proceedings will summarise the experience with the different interconnection techniques and performance tests of MALTA modules with 2 and 4 chips tested in a cosmic muon telescope. They will also show first results on the effect of serial power tests on chip performance as well as the impact of the different interconnection techniques and the results of mechanical tests. Finally, a conceptual study for a flex based ultra-light weight monolithic pixel module based on the MALTA chip with minimum interconnections is presented.

Review of Topside Interconnections for Wide Bandgap Power Semiconductor Packaging

Due to their superior material properties, wide bandgap (WBG) semiconductors enable the application of power electronics at higher temperature operation, higher frequencies, and higher efficiencies compared to silicon (Si). However, the commonly-used aluminum wire bonding as topside interconnection technology prevents WBG semiconductors from reaching their full potential, due to inherent parasitic inductances, large size, heat dissipation, and reliability issues of wire bonding technology. Therefore, this article presents a comprehensive review of topside interconnection technologies of WBG semiconductor power devices and modules. First, the challenges and driving factors for the interconnection of WBG semiconductor dies are discussed. Second, for each widely commercially used WBG semiconductor, i.e., silicon carbide and gallium nitride, technical details and innovative features of state-of-the-art interconnection techniques in packages are reviewed. Then, the majority of existing topside interconnection materials for WBG semiconductors are categorized and compared, followed by a discussion of their advantages, challenges, and failure modes. Based on this elaborate discussion, potential future directions of the interconnection technology development are given. It is concluded that the superior performance of WBG semiconductors can be obtained by combining novel materials with innovative designs for the topside interconnections.

A framework for comparing the energy production of photovoltaic modules using 2-, 3-, and 4-terminal tandem cells

Energy production, rather than efficiency, is the most important metric for comparing different configurations of tandem solar cells (2T, 3T, 4T), as each interconnection technique has its own advantages and disadvantages.

Delay and Power Efficient Technique for VLSI Interconnects

Delay and Power Efficient Technique for VLSI Interconnects

Large-Scale Distributed System and Design Methodology for Real-Time Cluster Services and Environments

The demand for a large-scale distributed system, such as a smart grid, which includes real-time interconnection, is rapidly increasing. To provide a seamless connected environment, real-time communication and optimal resource allocation of cluster microgrid platforms (CMPs) are essential. In this paper, we propose two techniques for real-time interconnection and optimal resource allocation for a large-scale distributed system. In particular, to configure a CMP, we analyze the data transfer rate and utilization rate from the intelligent electronic device (IED), collecting the power production data to the individual controller. The details provided in this paper are used to design a sample value, i.e., raw data transfer, on the basis of the IEC 61850 protocol for mapping. The choice of sampled values is to attain the critical time requirement, data transmission of current transformers, voltage transformers, and protective relaying of less than 1 s without complicating the real-time implementation. Furthermore, in this paper, a way to determine the optimal number of physical resources (i.e., CPU, memory, and network) for a given system is discussed. CPU ranged from 0.9 to 0.98 while each cluster increased from 10 to 1000. With the same condition, memory utilized almost 100% utilization from 0.98 to 1. Lastly, the network utilization rate was 0.96 and peaked at 1 at most. Based on the results, we confirm that a large-scale distributed system can provide a seamless monitoring service to distribute messages for each IED, and this can provide a configuration for CMP without exceeding 100% utilization.

Photovoltaic Energy Conversion System Integrated Into Unbalanced Distribution Electrical Networks Through Hardware in the Loop

In this article, a real-time, hardware in the loop (HIL) and experimental photovoltaic energy conversion system (PVECS) integrated into unbalanced distribution electrical networks is presented. Commonly, the three-phase voltages are not balanced, because the input–output of single-phase loads in low and medium voltage networks. In this context, the photovoltaic (PV) systems integration under the dq0-Frame control operation scheme, tend to generate current deformations. In contrast, a new control technique for PVECS interconnection is validated in a HIL scheme, even in the presence of unbalanced voltage. This new technique is considered simple and easy to implement, since it consists of a single PI control loop, guaranteeing reliable operation under unbalances voltage events. Thus, preserving favorable characteristics, such as: 1) always balanced currents; 2) low harmonic distortion; 3) unit power factor; and 4) Compliance with the rules of the network code. The PVECS effectiveness is assessed by complete mathematical model, the simulation results are evaluated using MATLAB-Simulink (MATLAB r2018, Mathworks, Natick, MA, USA), and the experimental results are validated with a small-scale prototype operating in a HIL environment and the real-time simulator Opal-RT Technologies (Montreal, QC, Canada); integrating a power capacity of 15 kW in distribution networks.