Channel plasmonic polariton (CPP) waveguides are a promising technology for integrated photonics. They offer several advantages over other plasmonic waveguides and are well-suited for various applications. In this research, a new design of asymmetric double-trenched CPP waveguide is suggested and examined. This design consists of two silicon trenches etched into a silicon dioxide substrate layer; with a gold layer sandwiched in between. The trenches are asymmetric, with one trench being wider than the other. This asymmetry creates a spatially varying surface plasmon polariton (SPP) field, which can guide light along the waveguide. The polarization characteristics of this proposed design are analyzed over a specific wavelength range (0.7 - 1.7 µm) to evaluate the mode confinement of the light within the structure. The design performance was optimized by changing the gold layer thickness and the dimensions of the lower trench. Different scenarios are examined to observe TE and TM-polarized modes’ behavior within the groove. A 1867.119 dB/µm suppression level at 0.92 µm wavelength is achieved which offers a small-size component for compact photonic logic gates, enabling the development of next-generation photonic devices.