Systolic Multiplier Research Articles

Low-Space Bit-Parallel Systolic Structure for AOP-Based Multiplier Suitable for Resource-Constrained IoT Edge Devices

Security and privacy issues with IoT edge devices hinder the application of IoT technology in many applications. Applying cryptographic protocols to edge devices is the perfect solution to security issues. Implementing these protocols on edge devices represents a significant challenge due to their limited resources. Finite-field multiplication is the core operation for most cryptographic protocols, and its efficient implementation has a remarkable impact on their performance. This article offers an efficient low-area and low-power one-dimensional bit-parallel systolic implementation for field multiplication in GF(2n) based on an irreducible all-one polynomial (AOP). We represented the adopted multiplication algorithm in the bit-level form to be able to extract its dependency graph (DG). We choose to apply specific scheduling and projection vectors to the DG to extract the bit-parallel systolic multiplier structure. In contrast with most of the previously published parallel structures, the proposed one has an area complexity of the order O(n) compared to the area complexity of the order of O(n2) for most parallel multiplier structures. The complexity analysis of the proposed multiplier structure shows that it exhibits a meaningful reduction in area compared to most of the compared parallel multipliers. To confirm the results of the complexity analysis, we performed an ASIC implementation of the proposed and the existing efficient multiplier structures using an ASIC CMOS library. The obtained ASIC synthesis report shows that the proposed multiplier structure displays significant savings in terms of its area, power consumption, area-delay product (ADP), and power-delay product (PDP). It offers average savings in space of nearly 33.7%, average savings in power consumption of 39.3%, average savings in ADP of 24.8%, and savings in PDP of 31.2% compared to the competitive existing multiplier structures. The achieved results make the proposed multiplier structure more suitable for utilization in resource-constrained devices such as IoT edge devices, smart cards, and other compact embedded devices.

Development of a device for multiplying numbers by means of FPGA

The authors propose the description of the development of a device for multiplying numbers. The device for multiplying numbers on the field-programmable gate array (FPGA) includes two input and one output registers, fifty-six single-digit adders, sixty four logic elements AND, one exclusive OR gate. The main scientific and technical task in developing a device for multiplying numbers is to reduce hardware complexity using single-bit adders and logic elements. Introduction includes description of works of scientists and researchers whose publications are devoted to design and development of multiplier construction methods, multiplier FIR performance improvement by right-shift and addition method on FPGA (field-programmable gate array) basis. The implementation of MAC-block, hardware implementation of binary multiplier on the basis of multi operand adder, multiplier design by right-sliding and addition with control automaton in the FPGA basis is the actual research tasks presented in a number of papers. The description of features of multiplier implementation, high-speed multipliers with variable bit rate, studies of approaches for designing modular multipliers, FPGA image processing using Brown multiplier for performing convolution operation find application in problems of performance and speed. Also, a number of authors describe implementation of conveyorization method, design of dual multiplier, construction method of 8-bit multiplier with reduced delay, 8-bit high-density systolic multiplier arrays on FPGA and development of high-performance 8-bit multiplier using McCMOS technology. A fragment of a developed device for multiplying numbers is presented in the work by the authors. The principle of operation of a device for multiplication is described. The description of connected elements of the device is given. The timing diagrams of operation of a device for multiplication of numbers are presented.

Low-latency area-efficient systolic bit-parallel GF(2[formula omitted]) multiplier for a narrow class of trinomials

Edge computing in Internet of Things (IoT) requires high-performance as well as cost-effective hardware implementations to accommodate large number of computations. Implementation of security in IoT edge devices is indispensable, and attaining security is possible using Elliptic curve cryptography (ECC) algorithms. Finite field GF(2m) multiplication is a performance-critical operation in these algorithms, hence, it requires efficient hardware implementations. Systolic structures for GF(2m) multiplier are suitable for high-performance applications as they allow high-throughput implementations. Many systolic GF(2m) multipliers have been proposed in the literature that can achieve high throughput rates, however, they require large area and high latency. In this paper, we propose a polynomial basis GF(2m) systolic multiplier applicable for a narrow class of trinomials which includes both the NIST (National Institute of Standards and Technology) recommended trinomials for m=233 and 409 fields. Analytical comparisons with the related multipliers for m=409 show that the multiplier proposed in this paper reduces the latency by 32% and area by 5%. The proposed multiplier is synthesized using synopsis tools targeting for an ASIC implementation and the comparisons are also presented. The proposed low-latency area-efficient multiplier can be used in the implementation of hardware security for low-cost IoT edge devices.

Low complexity design of bit parallel polynomial basis systolic multiplier using irreducible polynomials

Encryption schemes like AES require finite field modular multiplication. The encryption speed is highly dependent on the performance of the finite field multiplier. Several high-speed systolic bit parallel multipliers with low area complexity have been proposed in the literature. In this paper, a modular multiplication algorithm is used to propose a bit parallel polynomial basis systolic multiplier which has achieved 89% less and 17% less area-delay product than the best existing multipliers. It has been observed that the area complexity of the proposed systolic multiplier for irreducible polynomials matches with the best-reported multiplier with 17% less time complexity. The results are further verified with the help of the FPGA implementation of the proposed multiplier for m = 8,163. Being generic, the proposed multiplier can be optimized further for trinomials and pentanomials.

A low complexity bit parallel polynomial basis systolic multiplier for general irreducible polynomials and trinomials

The bit parallel multiplication scheme is characterized by an important feature called concurrency, which makes its execution faster. The output through this scheme is generated in every clock cycle, after taking ‘m’ clock cycles in the beginning. In this paper, a polynomial basis systolic multiplier over irreducible polynomials (xm+tm−1xm−1+....t2x2+t1x1+t0) in GF(2m) is designed specifically for odd ‘m’, which takes ‘m’ clock cycles and this is further, used to design the low complexity bit-parallel architecture for general irreducible polynomials and trinomials (xm+xk+1). The area complexity of the proposed multiplier for general irreducible polynomials matches with the best existing multiplier with a 17% reduction in time complexity due to a considerable decrease in critical path delay. To the best of our knowledge, the area-delay product of the proposed multipliers is the lowest achieved when compared with the best multipliers available in the literature. FPGA implementation results also show that the proposed multiplier has 59% less space complexity and 47% less time complexity than the best-reported multiplier for m = 233.

High-throughput area-delay-efficient systolic multiplier over GF(2m) for a class of trinomials

The paradigm of Edge Computing in Internet of Things (IoT) demands high-throughput implementations of IoT edge devices. Security algorithms used in these devices heavily use GF(2m) multiplications. Systolic structures for GF(2m) multipliers can offer high throughput rates along with other features such as regularity, concurrency, and modularity. Many systolic architectures for GF(2m) multiplier were proposed in the literature to achieve low area and time complexities. In this paper, we propose a high-throughput and low area-delay complexity systolic structure for the hardware realization of polynomial basis multiplication in GF(2m) for a class of trinomials. The complexity analysis shows that the proposed architecture results in achieving high throughput and less area-delay complexity compared with the existing polynomial basis multipliers in the literature. When compared with the best available multipliers, the multiplier realized using the proposed architecture achieves throughput improvement by 42% and reduction in area-delay product by 7% for m=409. Application specific integrated circuit (ASIC) implementations of the proposed multiplier and the best available multipliers confirm that the proposed multiplier outperforms the other multipliers. Hence, the proposed high-throughput area-delay-efficient multiplier can be employed in IoT edge devices.

Implementation of High Speed Low Power Systolic Multiplier Based on Irreducible Trinomials

This paper presents a high speed low power systolic multiplier based on irreducible trinomials which is implemented using GF (2M). To calculate a set of d partial products in each Handling Element (HE) during every cycle we suggest multiplication algorithm of digit level. By using the systolic channels independently, operands in the proposed structure will be reduced and accumulated by partial products. Functional verification (Simulation) of the multiplier is done by using Xilinx ISE and synthesis is done by using Xilinx XST. The synthesized design is implemented on Zynq7000 FPGA. After completion of the synthesis, it is found that the proposed multiplier achieved power consumption of 2.9mW. Area and the performance of the multiplier is optimized in the proposed structures.

Area-efficient low-latency polynomial basis finite field GF(2m) systolic multiplier for a class of trinomials

Many security and data reliability algorithms rely heavily on finite field GF(2m) arithmetic computations, in particular, multiplication. The design of a field multiplier employing systolic architecture is very much suited for very large scale integration (VLSI) implementation. Though systolic architecture gives higher throughput, it usually requires area overhead and high-latency. In this paper, we propose a systolic architecture for polynomial basis finite field GF(2m) multiplier based on a class of trinomials. Analysis shows that the proposed multiplier achieves low-area and low-latency compared to similar multipliers available in the literature. The proposed multiplier achieves 10% reduction in area complexity when compared with the best existing area-efficient multiplier, for m = 409. Application specific integrated circuit (ASIC) implementation of the proposed multiplier together with the two most comparable multipliers confirms that the proposed multiplier outperforms the other two multipliers with improvements in area and latency. The proposed area-efficient multiplier is suitable for Internet of Things edge-devices.

Design of Low Register all One Polynomial Multipliers Over GF (2m) on FPGA

This paper presents All-one-polynomial (AOP)- based systolic multipliers over GF (2m) need aid as a rule not acknowledged for useful execution for cryptosystems for example, elliptic bend cryptography (ECC) because of security motivations. Also that, systolic AOP multipliers typically suffer from those issue from the secondary register-complexity, particularly alongside field programmable gate array (FPGA) platforms the place the register assets need aid not that abundant. This paper however, we have demonstrated that those AOP-based systolic multipliers could effortlessly accomplish low registercomplexity usage and the recommended architectures could be utilized concerning illustration calculation cores with infer efficient usage from the systolic Montgomery multipliers In view of trinomials, which need aid recommended by the National institute of standard and technology (NIST) for cryptosystems. This paper, first we recommend a novel information television plan alongside which the register-complexity included inside existing AOP based systolic multipliers may be significantly decreased

Novel Pipelined Scalable Systolic Multiplier Based on Irreducible All-One Polynomials

A planned productive structure issued for the systolic execution of authoritative based limited field duplication over G F(2 m) in light of final 56-bit AOP is proposed in this work. We extricated a recursive increase calculation and utilized it to plan an intermittent and confined piece level reliance outline (DG) for systolic registering. The intermittent piece level DG is changed into a very smal grained DG, and the pipe coating is utilized for snappier mapping into a parallel systolic design. It doesn't require any overall correspondences for measured decline, in contrast to most current developments. The suggested bit-parallel systolic structure is similar to the parallel systolic structure, however the quantity of registers is altogether lower.

Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis

Efficient implementation of finite field multipliers based on a reordered normal basis (RNB) is highly desirable in the current/emerging cryptosystems since it offers almost free realization of squaring operation. Therefore, in this paper, we propose novel bit-parallel and digit-serial finite field multipliers over $GF(2^{m})$ based on RNB. By efficient transformation of the core multiplication algorithm using a unique circular shifting feature, we have derived an efficient algorithm for low-complexity systolic mapping. Both bit-parallel and digit-serial structures of the multipliers are then obtained and optimized to enhance the area–time efficiency. We have also utilized the unique feature of the proposed multiplication algorithm to obtain the systolic multipliers by Karatsubalike decomposition. Detailed analysis and comparison show the superior performance of the proposed implementation. For example, the proposed regular and Karatsuba-based bit-parallel designs involve at least 48.4% less area-delay product (ADP) and 42.2% less power-delay product (PDP) than the best existing ones (37.7% and 55.3% less ADP and PDP on field-programmable gate array platform), respectively. The proposed multipliers, because of their lower area–time complexities, can be used for efficient realization of cryptographic applications.

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach

Systolic finite field multiplier over $GF(2^{m})$ , because of its superior features such as high throughput and regularity, is highly desirable for many demanding cryptosystems. On the other side, however, obtaining high-performance systolic multiplier with relatively low hardware cost is still a challenging task due to the fact that the systolic structure usually involves large area complexity. Based on this consideration, in this paper, we propose to carry out two novel coherent interdependent efforts. First, a new digit-serial multiplication algorithm based on polynomial basis over binary field $(GF(2^{m}))$ is proposed. Novel Toeplitz matrix–vector product (TMVP)-based decomposition strategy is employed to derive an efficient subquadratic space complexity. Second, The proposed algorithm is then innovatively mapped into a low-complexity systolic multiplier, which involves less area-time complexities than the existing ones. A series of resource optimization techniques also has been applied on the multiplier which optimizes further the proposed design (it is the first report on digit-serial systolic multiplier based on TMVP approach covering all irreducible polynomials, to the best of our knowledge). The following complexity analysis and comparison confirm the efficiency of the proposed multiplier, that is, it has lower area-delay product (ADP) than the existing ones. The extension of the proposed multiplier for bit-parallel implementation is also considered in this paper.

Low‐complexity unidirectional systolic Dickson basis multiplier for lightweight cryptosystems

Finite field multiplier is a very important operation for realising elliptic curve cryptography. Dickson basis is a recently developed basis for representing finite elements in GF(2 m ). This study will propose a unidirectional systolic multiplier for such Dickson basis. The unidirectional systolic structure offers low space and time complexities and can be easily modified to have error detection capability which can resist side-channel attacks.

Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)

Because of the efficient tradeoff in area–time complexities, digit-serial systolic multiplier over G F ( 2 m ) has gained substantial attention in the research community for possible application in current/emerging cryptosystems. In general, this type of multiplier is designed to be applicable to one certain field-size, which in fact determines the actual security level of the cryptosystem and thus limits the flexibility of the operation of cryptographic applications. Based on this consideration, in this paper, we propose a novel hybrid-size digit-serial systolic multiplier which not only offers flexibility to operate in either pentanomial- or trinomial-based multiplications, but also has low-complexity implementation performance. Overall, we have made two interdependent efforts to carry out the proposed work. First, a novel algorithm is derived to formulate the mathematical idea of the hybrid-size realization. Then, a novel digit-serial structure is obtained after efficient mapping from the proposed algorithm. Finally, the complexity analysis and comparison are given to demonstrate the efficiency of the proposed multiplier, e.g., the proposed one has less area-delay product (ADP) than the best existing trinomial-based design. The proposed multiplier can be used as a standard intellectual property (IP) core in many cryptographic applications for flexible operation.

Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials

Digit-serial systolic multipliers over $GF(2^m)$ based on the National Institute of Standards and Technology (NIST) recommended trinomials play a critical role in the real-time operations of cryptosystems. Systolic multipliers over $GF(2^m)$ involve a large number of registers of size $O(m^2)$ which results in significant increase in area complexity. In this paper, we propose a novel low register-complexity digit-serial trinomial-based finite field multiplier. The proposed architecture is derived through two novel coherent interdependent stages: (i) derivation of an efficient hardware-oriented algorithm based on a novel input-operand feeding scheme and (ii) appropriate design of novel low register-complexity systolic structure based on the proposed algorithm. The extension of the proposed design to Karatsuba algorithm (KA)-based structure is also presented. The proposed design is synthesized for FPGA implementation and it is shown that it (the design based on regular multiplication process) could achieve more than 12.1 percent saving in area-delay product and nearly 2.8 percent saving in power-delay product. To the best of the authors’ knowledge, the register-complexity of proposed structure is so far the least among the competing designs for trinomial based systolic multipliers (for the same type of multiplication algorithm).

Design and Implementation of a Novel Bit-Parallel Systolic Multiplier Over GF(2m) for Irreducible Pentanomials

Cryptography in current digital world offers integrity and confidentiality of data being transferred over a communication network. Modern cryptography provides such security through cryptographic algorithms which mainly involve multiplication operation in finite fields. Since the finite field multiplication operation is a computationally intensive operation, various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. In this paper, a modified interleaved multiplication algorithm to perform multiplication of two finite field elements over GF(2m) for pentanomials is derived from a conventional interleaved multiplication algorithm using a novel Pre-Computation (PC) technique to reduce the computational complexity of the algorithm. Consequently, an m-bit systolic multiplier for pentanomials (SMP) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMP structure with similar multipliers available in the literature is presented. The SMP structure achieves about 28% improvement in hardware for [Formula: see text] when compared with the best multiplier available in the literature. The functionality of the proposed SMP structure is verified by implementing on a field-programmable gate array (FPGA) Virtex-7 (XC7V2000TFLG1925-2) prototype board and synthesizing in application specific integrated circuit (ASIC) using Synopsys Design Vision compiler with 90[Formula: see text]nm generic library. It can be observed from FPGA and ASIC implementation results that the proposed SMP structure shows improvement in area and power consumption when compared with similar multipliers available in the literature.

Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over <inline-formula> <tex-math notation="LaTeX">$\textit{GF}(2^{m})$ </tex-math> </inline-formula>

Systolic finite field multiplier over $\textit {GF}(2^{m})$ based on the National Institute of Standards and Technology (NIST) recommended pentanomials or trinomials can be used as a critical component in many cryptosystems. In this paper, for the first time, we propose a novel low-complexity unified (hybrid field size) systolic multiplier for NIST pentanomials and trinomials over $\textit {GF}(2^{m})$ . We have proposed a computation-core-based design strategy to obtain the desired low-complexity unified multiplier for both NIST pentanomials and trinomials. The proposed multiplier can swift between pentanomial-based and trinomial-based multipliers through a control signal. First of all, a novel strategy is briefly introduced to implement a certain matrix-vector multiplication, which can be packed as a standard computation core (or computation core like). Then, based on the computation-core concept, a novel unified multiplication algorithm is derived that it can realize both the pentanomial-based and trinomial-based multiplications. After that, an efficient systolic structure is presented that it can fully employ the introduced computation core. A detailed example of the proposed unified multiplier (for $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ ) is also presented. Both the theoretical and field-programmable gate array implementation results show that the proposed design has efficient performance in area-time-power complexities, e.g., the proposed design (the one performs $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ multiplications) is found to have at least 14.2% and 13.3% less area-delay product and power-delay product than the combination of the existing individual $\textit {GF}(2^{163})$ and $\textit {GF}(2^{233})$ multipliers (best among all competing designs), respectively. Because of its structural regularity and functional flexibility, the proposed unified multiplier can be used as an intellectual property core for various cryptosystems.

Bit‐parallel systolic multiplier over for irreducible trinomials with ASIC and FPGA implementations

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre-computation (PC) technique to perform multiplication over for trinomials. Consequently, an m-bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves ∼28 and 17% improvement in hardware and area-delay product, respectively, for m = 233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area-delay, and power-delay products when compared with similar multipliers available in the literature.

Systolic array multiplier for augmenting data center networks communication link

The paper will present a heuristic architecture that is used for the systolic array multiplier for the delay and power—the delay product minimization using various input bit sizes. Systolic architecture maps high-level computation into hardware structures. As these have regularity and can be easily reckoned, the systolic systems are easy to implement. This architecture results in cost effective, better performance and special purpose systems that can solve a wide variety of problems. An effective method for designing Very Large Scale Integration (VLSI) architecture that is based on the proper decomposition technique that uses circular correlations has been presented. Here the multiplication is a commonly used operation in both Mathematics and also in Digital Signal Processing applications. The Systolic algorithm will be an efficient algorithm that performs binary multiplication and the Systolic architectures will provide better performance in design like that of the multiplier, matrix multiplication, the Finite Impulse Response based filter and also the Distributed Array Arithmetic. This work proposed a VLSI architecture based on systolic multiplier that can be implemented on Network links to reduce energy consumption. The proposed work concentrate on the development of a novel architecture having decomposition cells used for the systolic multiplier. There are two different architectures that are proposed and among them the Architecture-I has been designed having the decomposition cells along with registers in case of the feed forward path delay for the delay minimization. This proposed work has resulted in the delay reduction of about 32% that is compared to the existing work. In the architecture-II and their Processing Elements that have been designed along with the tristate buffers and also the multiplexer that is based on the full adder in power minimization. Their results in a lower power delay based product of about 6% compared to the current work and the Field Programmable Gate Array tested proved the delay and the improvement of power-delay product compared to other conventional architectures.

Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2 m ) for Irreducible Polynomials

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.