System-on-chip Platform Research Articles

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms

The complexity of modern system-on-chip (SoC) designs and the ever shortened time-to-market (TTM) makes the third-party intellectual property (3PIP) a cornerstone in the modern SoC supply chain. Various 3PIPs are involved in modern SoCs, performing functionality ranging from computation accelerating to sensitive data processing. The wide use of 3PIPs also raises security concerns, e.g., hardware Trojans inserted in 3PIPs may compromise the security of the whole system. While SoC integrators carefully evaluate the functionality of the acquired 3PIPs, there lack effective and low-cost solutions for third-party IP security validation in the SoC environment. Exacerbating the issue, Trojans may be located in multiple IPs and will only perform malicious tasks collaboratively. To address these limitations and to protect modern SoCs, we propose a runtime 3PIP Trojan detection framework. The new framework, named IP-Tag, is a tag-based structure to track the requests on SoC and enforce fine-grained access control in individual IPs. The proposed framework can detect and prevent illegal access and sensitive data leakage on IPs within the SoC environment. The proposed IP-Tag framework was demonstrated on an RISC-V-based SoC and also implemented on an FPGA platform for security and performance analysis. Our experimental results show that the developed IP-Tag can detect and prevent illegal access and sensitive data leakage in SoC with malicious IPs. The hardware overhead is 7.9% LUTs and 7.8% Flip-Flops and a performance overhead is 2.2%.

Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications

The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard version of the AMBA APB bus to connect peripherals and is primarily geared towards control and monitoring applications. This solution is a demonstrator of what can become a more complete fully radiation-tolerant SoC platform with a standardized interconnect and an IP block library, to serve as the starting point for future ASIC designs. The ASIP based approach targets more the design of data path elements and the use in data processing applications. The presented approach makes use of a commercial ASIP Designer EDA tool to demonstrate an integrated workflow to define, benchmark and optimize an ASIP for a specific use case, starting from a general-purpose processor.

Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform

In the process of NIST postquantum cryptography standardization, module lattice-based Dilithium has been chosen as one of the three third-round finalists for digital signature schemes. More evaluations of its implementation efficiency on different platforms are required for further competition. In this article, we present an efficient implementation of Dilithium on a field-programmable gate array (FPGA) system-on-chip (SoC) platform. To achieve a high computation speed, we design a hardware architecture to perform the main body of the algorithm, and the preprocessing and postprocessing steps are accomplished by the processor. For the hardware architecture, we take some optimizations on the most time-consuming operations, that is, polynomial multiplication, hashing, and sampling. Polynomial multiplications are accelerated by the radix-4 number theoretic transform (NTT) architecture with a conflict-free memory mapping scheme. A fast modular multiplication on the Dilithium modulus is proposed to support the underlying calculations. For hashing and sampling, we design a multipurpose hashing unit and a compact sampling unit. The cooperative work of the two units accelerates the sampling process significantly. We implement the Key Generation, Signing, and Verification algorithms of the round-3 Dilithium at all three security levels on the Xilinx Zynq-7000 platform. Compared with existing software/hardware codesign for Dilithium on a similar platform, our design achieves about <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$17\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40\times $ </tex-math></inline-formula> improvements in performance for the Signing and Verification algorithms, respectively, at the cost of about <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7.8\times $ </tex-math></inline-formula> more look up table (LUT) resources.

Fast, closed-loop iterative system-on-chip of deflection efficiency enhancement for a liquid crystal optical phased array.

To implement a liquid crystal optical phased array (LC-OPA) on a practical free-space laser communication terminal, there are two essential parameters: insertion loss and the closed-loop bandwidth required to meet the dynamic linking condition of the acquisition-tracking-pointing sub-system. Real-time hardware platforms and deflection efficiency optimization algorithms have been suggested since the invention of LC-OPA. In this paper, the so-called ZYNQ platform, a field-programmable-gate-array-based heterogeneous system-on-chip (SoC), is utilized to keep real-time response and accelerate data generation, such as beam steering, beamforming, beam enhancement, etc. In addition, a novel, to the best of our knowledge, optimization algorithm is proposed on the concept of dimension reduction of the number of objective variables. After deploying on this heterogeneous SoC platform, numerical simulations and experimental results both verify that, compared to the conventional PC-based system, the integrated SoC platform offers 15.8 times faster iterative speed, a rapid convergence rate, and excellent robustness, yet with less usage of power, physical size, and monetary cost. The efficiency enhancement process costs only a few seconds at any angle, laying the foundation for practical in-line applications.

Hardware and software co-verification from security perspective in SoC platforms

Attacks which combine software and hardware vulnerabilities are emerging security problems. Although runtime verification or remote attestation can determine the correctness of program states on a processor core, existing methods rarely consider the software states on the whole System on Chip (SoC). Also, there are SoC level solutions focusing on addressing the threat in the RISC-V architecture, which provides an open Instruction Set Architecture (ISA) of the processor. In this paper, we propose a comprehensive software and hardware co-verification method to protect the entire RISC-V based SoC platform at runtime. The proposed method adopts the Dynamic Information Flow Tracking (DIFT) framework to implement a new Verifier and Prover security architecture for supporting runtime software and hardware co-verification. This framework also considers the security states of third-party IPs (3PIPs). The framework is implemented as a coprocessor, new bus and DIFT supported IP wrapper which does not change the architecture of the main processor core. The new security architecture can be integrated with other RISC-V processors. We implement a FPGA prototype on the Rocket-Chip, an RISC-V open-source processor core. The hardware overhead is 10% LUTs and 9.4% Flip-Flops and a performance overhead is 3%.

Ses Efektlerine Özel Yüksek Seviye Hızlandırıcılarla Düşük Gecikmeli SoC Tasarımı

High-quality sound processing requires hardware acceleration in order to reduce the processing latency of the applied effect over the sound. Computational latency of creating enhanced sound from the audio input is an important delay component and affects the performance especially in artists’ live performance or high-quality sound generation. Artists want to apply a sound effect on their music and latency is the main problem when these systems running in real-time. CPU-based systems present flexibility, but introduce a high amount of latency while processing, which in fact affects the artist negatively. In this study, to get the flexibility through software and the acceleration via hardware specialization, we present a system-on-chip (SoC) solution with HW/SW co-design methodology for sound-effects. We reduce the latency and increase the frequency by applying pipelining through MATLAB. The system is implemented and tested on programmable SoC platform, ZedBoard, which contains ZC7020 Zynq chip with a dual-core ARM-Cortex-A9 processor. The ARM processor enables the management of sound-effect hardware accelerator running on FPGA and communication with user. Sound effect is designed with block models provided by MATLAB &amp;amp; Simulink. HDL Coder converts these blocks into RTL-level hardware designs. The followed design methodology provided by MATLAB &amp;amp; Simulink enables high-level block design that can be embedded into FPGA at RTL-level to benefit from the speed provided by high-speed hardware registers and to have an AXI interconnect interfacing with software in order to utilize the software flexibility. The study shows that latency is reduced significantly.

A scalable and efficient convolutional neural network accelerator using HLS for a system-on-chip design

This paper presents a configurable convolutional neural network accelerator (CNNA) for a system-on-chip (SoC). The goal was to accelerate inference in different deep learning networks on an embedded SoC platform. The presented CNNA has a scalable architecture that uses high-level synthesis (HLS) and SystemC for the hardware accelerator. It can accelerate any convolutional neural network (CNN) exported from Keras in Python and supports a combination of convolutional, max-pooling, and fully connected layers. A training method with fixed-point quantised weights is proposed and presented in the paper. The CNNA is template-based, enabling it to scale for different targets of the Xilinx Zynq platform. This approach enables design space exploration, which makes it possible to explore several configurations of the CNNA during C and RTL simulation, fitting it to the desired platform and model. The CNN VGG16 was used to test the solution on a Xilinx Ultra96 board using productivity for Zynq (PYNQ). The result gave a high level of accuracy in training with an autoscaled fixed-point Q2.14 format compared to a similar floating-point model. It was able to perform inference in 2.0 s while having an average power consumption of 2.63 W, which corresponds to a power efficiency of 6.0 GOPS/W.

Remote Laboratory for E-Learning of Systems on Chip and Their Applications to Nuclear and Scientific Instrumentation

Configuring and setting up a remote access laboratory for an advanced online school on fully programmable System-on-Chip (SoC) proved to be an outstanding challenge. The school, jointly organized by the International Centre for Theoretical Physics (ICTP) and the International Atomic Energy Agency (IAEA), focused on SoC and its applications to nuclear and scientific instrumentation and was mainly addressed to physicists, computer scientists and engineers from developing countries. The use of e-learning tools, which some of them adopted and others developed, allowed the school participants to directly access both integrated development environment software and programmable SoC platforms. This facilitated the follow-up of all proposed exercises and the final project. During the four weeks of the training activity, we faced and overcame different technology and communication challenges, whose solutions we describe in detail together with dedicated tools and design methodology. We finally present a summary of the gained experience and an assessment of the results we achieved, addressed to those who foresee to organize similar initiatives using e-learning for advanced training with remote access to SoC platforms.

Hardware-software partitioning using three-level hybrid algorithm for system-on-chip platform

This study discusses hardware-software partitioning, which is useful for system-on-chip (SoC) applications. Hardware-software partitioning attempts to obtain the lowest execution time by combining a hardware processor system and a field programmable gate array on the SoC platform in embedded system applications. A three-level hybrid algorithm called GAGAPSO is proposed in this study. The algorithm consists of two successive genetic algorithms (GAs) and one particle swarm optimization (PSO). The drawbacks of these two algorithms are GA has low convergence speed and PSO has premature convergence because of low diversity. These algorithms are combined in this study to achieve high-capacity global convergence and enhanced search efficiency. In this study, three algorithms are developed, namely, GA, GAPSO and GAGAPSO using MATLAB. These algorithms are evaluated on the basis of the number of nodes and the minimum cost that can be achieved. The number of nodes varies from 10 to 1000 nodes. The minimum cost and the number of iterations to achieve the minimum cost are recorded. Results show that GAGAPSO can converge faster than GA and GAPSO. Furthermore, GAGAPSO can achieve the lowest cost for all nodes.

Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes

Ranging from circuit-level characterization to designing a platform architecture, developing a design automation tool, and fabricating a System on Chip (SoC), this article deals with the entire development process for ultralow-power (ULP) SoCs for Internet-of-Things (IoT) end nodes. More precisely, this article first focuses on the unique characteristics of the ULP circuits, the temperature effect inversion (TEI), i.e., the delay of the ULP circuits decreases with increasing temperature. Existing TEI-aware low-power (TEI-LP) techniques have incredible potential to further reduce the power consumption of conventional ULP SoCs, but there is a critical limitation to be widely adopted in real SoCs. To address this limitation and realize the ULP SoCs that can fully benefit from the TEI-LP techniques, this article proposes a new TEI-inspired SoC platform (TIP) architecture. On top of that, taking into account that the highly complex, time consuming, and labor-intensive development process of these ULP SoCs may hinder their widespread use for IoT end nodes, this article presents a new electronic design automation tool to accelerate ULP SoC development, RISC-V express (RVX). Finally, by using the RVX, this article introduces a TIP prototyping chip fabricated in 28-nm FD-SOI technology. This chip demonstrates that power savings of up to 35% can be achieved by lowering the supply voltage from 0.54 to 0.48 V at 25 °C and 0.44 V at 80 °C while continuing to operate at a target 50-MHz clock frequency.

Software-Defined Radio Transceiver Design Using FPGA-Based System-on-Chip Embedded Platform With Adaptive Digital Predistortion

In this paper, a software-defined radio (SDR) based transceiver system is designed and implemented on the system-on-chip (SoC) platform, which consists of a high-speed Arm embedded processor and a reconfigurable field-programmable gate array (FPGA). In the proposed SDR transceiver, the real-time baseband signal generation and adaptive digital predistortion (ADPD) units are implemented on the SoC platform. Memory polynomial model based ADPD solution is implemented to linearize the radio frequency (RF) power amplifiers (PAs). The implementation of the ADPD on a reconfigurable FPGA platform makes the system flexible and cost-effective. The PA characterization, in terms of model extraction and coefficient calculation, is done in real-time. These calculated coefficients are updated in the transmission path to precondition the transmitted signal before it is applied to the PA. The proposed ADPD is applied at the baseband level. Therefore, it can be used for different classes of PA operating at different RF carrier frequencies. A long-term evolution (LTE) signal with 20 MHz bandwidth and 11 dB peak to average power ratio (PAPR) is used for simulation and measurement purposes. The LTE signal is amplified using a GaN-based harmonically tuned continuous Class-F PA in measurement. The performance of the implemented ADPD scheme is analyzed in terms of NMSE, ACPR and EVM.

Parameter Extraction of PSP MOSFET Model in Multi-core Zynq SoC Platform

Abstract Zynq System on Chip (SoC) is widely used architecture to accelerate the computational intensive application with its ARM Processing System (PS) and FPGA fabric - Programmable Logic (PL). In this paper, parameter extraction of PSP MOSFET model is studied as a computational intensive process and its function is accelerated by HW/SW co-design on Zynq SoC using its dual-core Asymmetric Multiprocessing (AMP) architecture. Particle Swarm Optimization (PSO) algorithm is being applied to extract PSP model parameters in order to accurately match the model generated response with measured characteristic. This paper presents the acceleration model for two major processes of parameter extraction: 1) Optimization algorithm (PSO), and 2) Model library (SiMKit) execution. First, the PSO algorithm is implemented as hardware on PL. Second, PSP MOSFET library SiMKit is implemented as a software on PS. Implementation results show 73.06% improvement in PSO execution time compared to ARM-based software implementation. Dual-core AMP configuration results into 28.54% better performance in SiMKit execution time compared to a single-core processor.

SoC Hardware Implementation of Real-Time Video Segmentation based on the Mixture of Gaussian Algorithm

Video segmentation based on the Mixture of Gaussian (MoG) algorithm is widely used in video processing systems, and hardware implementations have been proposed in the past years. Most previous work focused on high-performance custom design of the MoG algorithm to meet real-time requirement of high-frame-rate high-resolution video segmentation tasks. This paper focuses on the System-on-Chip (SoC) design and the priority is SoC integration of the system for flexibility/adaptability, while at the same time, custom design of the original MoG algorithm is included. To maximally retain the accuracy of the MoG algorithm for best segmentation performance, we minimally modified the MoG algorithm for hardware implementation at the cost of hardware resources. The MoG algorithm is custom-implemented as a hardware IP (Intellectual Property), which is then integrated within an SoC platform together with other video processing components, so that some key control parameters can be configured on-line, which makes the video segmentation system most suitable for different scenarios. The proposed implementation has been demonstrated and tested on a Xilinx Spartan-3A DSP Video Starter Board. Experiment results show that under a clock frequency of 25 MHz, this design meets the real-time requirement for VGA resolution (640 × 480) at 30 fps (frame-per-second).

Power analysis approach and its application to IP-based SoC design

Purpose Low-power consumption has become an important issue that cannot be ignored in System-on-Chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. This paper aims at demonstrating an accurate and fast power estimation technique. Design/methodology/approach The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented Genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Findings The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. In experiments, the average error is estimated at 13.84%. Research limitations/implications To present the research findings with clarity and to avoid complexities, the paper does not consider delay factors like glitches, jitter etc. in the power model. Practical implications The proposed methodology allowed accurate power/energy analysis of practical applications mapped onto Network-on-Chip (NoC) based Multiprocessors SoC platform. It enables the performance analysis of different design alternatives under the load imposed by complex applications. Originality/value This paper is an original contribution and the results demonstrate that our novel technique could be implemented to achieve fast and accurate power estimation in the early stage of any SoC design.

Fabricating in-plane transistor and memory using atomic force microscope lithography towards graphene system on chip

Recently, various electronic components including transistor, barristor, memory, and transparent electrode were implemented using graphene. While integrated circuits were demonstrated by combining graphene transistors and passive components, system on chip (SoC) platform, state-of-the-art semiconductor technology, by combining transistors and memories on the same chip, has not yet been demonstrated. The main obstacle of the realization of SoC is the complexity of fabrication processes originated from the process differences between the transistors and the memories. In this study, using simple and clean atomic force microscope lithography, we fabricated both the switching devices and the memories by forming very thin graphene oxide (GO) barriers in mono-layer graphene at the controlled oxidation voltages. Formed with 7 V and 9 V, the lateral graphene/GO/graphene junction devices exhibit switching of Fowler-Nordheim tunneling current and resistive memory behavior, respectively. The combination of high on/off current ratio (∼1000) of the switching device and nonvolatility of the memory device fabricated by the same process demonstrates the possibility of graphene SoC platform.

System-on-Chip-based highly integrated Powertrain Control Unit for next-generation Electric Vehicles: harnessing the potential of Hybrid Embedded Platforms for Advanced Model-Based Control Algorithms

In this paper, a novel highly integrated System on Chip (SoC) based control unit concept is presented, which is conceived to combine the functionality of various powertrain ECUs and to additionally enhance their control with predictions based on the real-time execution of complex mathematical models. Such a platform has the potential for providing considerable benefits to upcoming hybrid and electric vehicles, especially for highly complex and efficient hybrid and multi-motor electric vehicles. A clear advantage is the reduction of Control Units, consequently also reducing the system complexity, communication requirements and development effort, which are directly associated to production and development costs. A controller architecture capable of exploiting the strength intrinsic to the nature of each platform type is presented, basing on the new generation of high-performance hybrid SoC platforms which combine powerful processors with cutting edge FPGAs. The parallel hardware paradigm of FPGAs enables the implementation into a single component not only of several Field Oriented Control loops for electrical motors, power management functions and vehicle-level optimizations, but also of advanced real-time predictive algorithms. The combination of so many complex tasks would not be feasible on a typical automotive microcontroller unit. A further objective for obtaining a highly integrated solution is to establish an efficient development and prototyping process, aiming to simplify and harmonize the workflow through the whole V model, by completely basing it on model-based-design tools. Finally, the concept demonstrator being implemented in this paper will combine a state-of-the-art high performance microprocessor and FPGA using a commercial SoC platform together with model-based software development tools. This will also fulfil the expectation of providing a topology with great migration and industrialization potential for the case of higher qualification requirements. Furthermore, it is another step towards a necessary mindset shift on control system development and integration methods for increasingly complex vehicles.

Development of Handheld Cardiac Event Monitoring System

This paper contributes the development, prototyping and analysis of proposed methodology on ARM (Advanced RISC Machine) in laboratory for automatic detection of arrhythmia beat in real-time for diagnosis of cardiovascular diseases. The methodology involves the integration of R peak detection algorithm, Principal Component Analysis for feature extraction and feedforward neural network architecture to classify generic heartbeats into six classes. The proposed methodology is implemented on ARM-based SoC (System-on-Chip) platform for diagnosis of six heartbeats. This developed system is validated by generating realtime ECG beats using MIT-BIH database and the output of the proposed system is monitored in the displaying device. The performance metrics of the developed system yields an overall accuracy of 92.81% with average sensitivity, specificity and positive predictivity of 92.68%, 98.51% and 92.42% respectively. Moreover, the developed system can be fabricated into a handheld device for automatic ECG beat monitoring.

SoC based floating point implementation of differential evolution algorithm using FPGA

This paper presents floating point design and implementation of System on Chip (SoC) based Differential Evolution (DE) algorithm using Xilinx Virtex-5 Field Programmable Gate Array (FPGA). The hardware implementation is carried out to enhance the execution speed of the embedded applications. Intellectual Property (IP) of DE algorithm is developed and interfaced with the 32-bit PowerPC 440 processor using processor local bus (PLB) of Xilinx Virtex-5 FPGA. In the proposed architecture the algorithmic parameters of DE are scalable. The software and hardware implementation of the DE algorithm is carried out in PowerPC embedded processor and hardware IP respectively. The optimization of numerical benchmark functions and system identification in control systems are implemented to verify the proposed hardware SoC platform. The performance of the IP is measured in terms of acceleration gain of the DE algorithm. The optimization problems are solved by using floating point arithmetic in both embedded processor and hardware. The experimental result concludes that the hardware DE IP accelerates the execution speed approximately by 200 times compared to equivalent software implementation of DE algorithm on PowerPC 440 processor. Further, as a case study an Infinite Impulse Response (IIR) based system identification task on SoC using the developed hardware accelerator is implemented.

Monitoring transaction level SystemC models using a generic and aspect-oriented framework

Transaction level modelling (TLM) is gaining acceptance as a way to create hardware designs at high abstraction levels. It allows better simulation performances and early prototyping for system-on-chip (SoC) designs. Transaction level models are therefore increasingly being used as golden references. In this paper, we present a new framework for the verification of properties of SystemC transaction level models during simulation. Functional as well as performance properties are addressed. Aspect-oriented programming (AOP) techniques are exploited to monitor the design under verification in an automated way and to write assertion checkers that fit TLM requirements. In addition, we propose a generic SystemC implementation approach that allows the specification and validation of fully-parameterisable transaction level properties. We illustrate our work on a realistic multi-level SoC platform based on the TLM-2.0 standard and including Open Core Protocol (OCP) interfaces.