Hardware-software partitioning using three-level hybrid algorithm for system-on-chip platform

Tiong Reng Xian,Zaini Abdul Halim,Ching Chia Leong,Tan Jiunn Gim

doi:10.11591/eei.v10i1.2201

Abstract

This study discusses hardware-software partitioning, which is useful for system-on-chip (SoC) applications. Hardware-software partitioning attempts to obtain the lowest execution time by combining a hardware processor system and a field programmable gate array on the SoC platform in embedded system applications. A three-level hybrid algorithm called GAGAPSO is proposed in this study. The algorithm consists of two successive genetic algorithms (GAs) and one particle swarm optimization (PSO). The drawbacks of these two algorithms are GA has low convergence speed and PSO has premature convergence because of low diversity. These algorithms are combined in this study to achieve high-capacity global convergence and enhanced search efficiency. In this study, three algorithms are developed, namely, GA, GAPSO and GAGAPSO using MATLAB. These algorithms are evaluated on the basis of the number of nodes and the minimum cost that can be achieved. The number of nodes varies from 10 to 1000 nodes. The minimum cost and the number of iterations to achieve the minimum cost are recorded. Results show that GAGAPSO can converge faster than GA and GAPSO. Furthermore, GAGAPSO can achieve the lowest cost for all nodes.

Highlights

System on chip (SoC) is one of the platforms in the current embedded system design
Hardware-software partitioning is proposed for the combination of field programmable gate array (FPGA) and hardware processor system (HPS) in embedded system applications to require few resources and reduce the power consumption and execution time
The GAGAPSO has a smooth graph with few iterations to achieve the minimum cost

Summary

Introduction

System on chip (SoC) is one of the platforms in the current embedded system design. Like low power consumption, light weight and small size, have made it popular in current applications of embedded system design. SoC consists of a field programmable gate array (FPGA) and a hardware processor system (HPS). Hardware refers to the FPGA that runs as parallel circuits, whereas software refers to the HPS that executes sequential instructions. FPGA tends to improve the execution time through its parallel processing capability but uses many resources [1], which lead to high power consumption. Hardware-software partitioning is proposed for the combination of FPGA and HPS in embedded system applications to require few resources and reduce the power consumption and execution time

Methods

Results

Conclusion