System-on-chip Platform Research Articles

CoMoSy: a Flexible System-on-Chip Platform for Embedded Applications

Thanks to the rapid evolution of semiconduc-tor technology, System-on-Chip (SoC) paradigm has be-come one of the most common design methodologies for quickly developing embedded systems to meet the high demands of embedded applications. In this paper, we present the design and implementation on a SoC platform targeted to controlling and monitoring applications. This proposed platform is composed of a 32-bit processor and a dozen of common hardware interfaces, providing the programmability and connectivity to peripheral devices such as memories, Lan network, monitor, keyboard, ADC, DAC, or other I/O device. In addtion, to increase the flexibility of the system and to rapidly develop end-user applications, we also deploy an application-specific software framework with the robustness of a lightweight kernel and real-time applet management. The system model has finally been validated through the realization of a remote control camera system.

Analysis of Verification Methodologies Based on a SoC Platform Design

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

Programmable System-on-Chip for Silicon Prototyping

This paper presents a programmable system-on-chip (SoC) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing a common SoC platform. In this implementation, an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , while the area of the integrated platform is about 24.43 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13-μm CMOS generic logic process technology.

Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform

Due to recent advances in high dynamic range (HDR) technologies, the ability to display HDR images or videos on conventional LCD devices has become more and more important. Many tone-mapping algorithms have been proposed to meet this end, the choice of which depends on display characteristics such as luminance range, contrast ratio and gamma correction. An ideal HDR tone-mapping processor should have a robust core functionality, high flexibility, and low area consumption, and therefore an ARM-core-based system-on-chip (SOC) platform with a HDR tone-mapping application-specific integrated circuit (ASIC) is suitable for such applications. In this paper, we present a systematic methodology for the development of a tone-mapping processor of optimized architecture using an ARM SOC platform, and illustrate the use of this novel HDR tone-mapping processor for both photographic and gradient compression. Optimization is achieved through four major steps: common module extraction, computation power enhancement, hardware/software partition, and cost function analysis. Based on the proposed scheme, we present an integrated photographic and gradient tone-mapping processor that can be configured for different applications. This newly-developed processor can process 1,024 × 768 images at 60 fps, runs at 100 MHz clock and consumes a core area of 8.1 mm2 under TSMC 0.13 μm technology, resulting in a 50% improvement in speed and area as compared with previously-described processors.

Integrating real-time inter-task communication channels into hardware–software codesign

Codesign in system on chip (SoC) systems is a joint development of hardware and software tasks to obtain a complete system design. Especially, a key problem in the hardware–software codesign for real-time embedded systems is related to the time-bounded communication channel that guarantees the deadlines of tasks, as well as the timely delivery of messages exchanged between tasks. This paper presents a technique to integrate a real-time inter-task communication channel into hardware–software codesign. The real-time inter-task communication channel presented in this paper is addressed from two perspectives: a unified inter-task communication interface and a combined task and message scheduling scheme. From the perspective of an inter-task communication interface, we consider three possible inter-task communication associations, software-to-software, software-to-hardware, and hardware-to-hardware task communication associations. Tasks and messages exploited in real-time inter-task communications are allowed to have periodic and aperiodic properties. In the unified inter-task communication interface, coarse-grained real-time processing is allowed at a level of task unit and fine-grained real-time processing is allowed at a piece of message frame unit. Consequently, periodic tasks and messages need to be timely processed and delivered to meet their deadlines, and aperiodic tasks and messages need to be quickly processed for fast response without missing periodic task and message deadlines. We present a novel scheduling policy from the perspective of the combined task and message scheduling scheme. In the scheduling policy, the first objective is to meet the timing constraints of periodic tasks as well as periodic messages simultaneously for given application-specific real-time requirements. The second objective is to improve the response time of aperiodic messages. We evaluated the performance of the proposed technique after implementing it on a commercial SoC platform. The experimental evaluation showed it yielded efficient performance in terms of the minimal deadline miss ratio of periodic tasks and messages, and a fast average response time for aperiodic messages.

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

With the rapid development of semiconductor technology, more complicated systems have been integrated into single chips. However, system performance is not increased in proportion to the gate-count of the system. This is mainly because the optimized design of the system becomes more difficult as the systems become more complicated. Therefore, it is essential to understand the internal behavior of the system and utilize the system resources effectively in the System on Chip (SOC) design. In this paper, we design a Performance Analysis Unit (PAU) for monitoring the AMBA Advanced eXtensible Interface (AXI) bus as a mechanism to investigate the internal and dynamic behavior of an SOC, especially for internal bus activities. A case study with the PAU for an H.264 decoder application is also presented to show how the PAU is utilized in SOC platform. The PAU has the capability to measure major system performance metrics, such as bus latency, amount of bus traffic, contention between master/slave devices, and bus utilization for specific durations. This paper also presents a distributor and synchronization method to connect multiple PAUs to monitor multiple internal buses of large SOC.

Dynamically reconfigurable hardware–software architecture for partitioning networking functions on the SoC platform

We present an issue of the dynamically reconfigurable hardware–software architecture which allows for partitioning networking functions on a SoC (System on Chip) platform. We address this issue as a partition problem of implementing network protocol functions into dynamically reconfigurable hardware and software modules. Such a partitioning technique can improve the co-design productivity of hardware and software modules. Practically, the proposed partitioning technique, which is called the ITC (Inter-Task Communication) technique incorporating the RT-IJC 2 (Real-Time Inter-Job Communication Channel), makes it possible to resolve the issue of partitioning networking functions into hardware and software modules on the SoC platform. Additionally, the proposed partitioning technique can support the modularity and reuse of complex network protocol functions, enabling a higher level of abstraction of future network protocol specifications onto the SoC platform. Especially, the RT-IJC 2 allows for more complex data transfers between hardware and software tasks as well as provides real-time data processing simultaneously for given application-specific real-time requirements. We conduct a variety of experiments to illustrate the application and efficiency of the proposed technique after implementing it on a commercial SoC platform based on the Altera’s Excalibur including the ARM922T core and up to 1 million gates of programmable logic.

An MDDI-Host Architecture with Low Complexity for SoC Platforms

This paper proposes a low-complexity mobile display digital interface (MDDI) architecture. We implement and verify the proposed MDDI-host architecture on a system-on-chip (SoC) platform with a 32-bit RISC CPU and a FPGA module. As a result of verification, the gate count of the MDDI host is reduced by about 50 % compared to that of the conventional parallel interface. And the bandwidth per pin of the MDDI host is 3 times more than that of a conventional parallel interface. Furthermore, the MDDI host that we implement includes the advanced high-performance bus (AHB) interface. Therefore, the proposed MDDI architecture is suitable for SoC platforms .

Designing efficient irregular networks for heterogeneous systems-on-chip

Networks-on-chip will serve as the central integration platform in future complex systems-on-chip (SoC) designs, composed of a large number of heterogeneous processing resources. Most researchers advocate the use of traditional regular networks like meshes, tori or trees as architectural templates which gained a high popularity in general-purpose parallel computing. However, most SoC platforms are special-purpose tailored to the domain-specific requirements of their application. They are usually built from a large diversity of heterogeneous components which communicate in a very specific, mostly irregular way. In this work, we propose a methodology for the design of customized irregular networks-on-chip, called INoC. We take advantage of a priori knowledge of the communication characteristic of the application to generate an optimized network topology and routing algorithm. We show that customized irregular networks are clearly superior to traditional regular architectures in terms of performance at comparable implementation costs for irregular workloads. Even more, they inherently offer a high degree of scalability and expansibility which allows to adapt the network to an arbitrary number of nodes with a given communication demand. This can normally not be accomplished by traditional approaches.

SoC 플랫폼 상에서 임베디드 블루투스 오디오 스트리밍 솔루션 개발

본 논문에서는 블루투스 무선 링크를 이용한 실시간 오디오 스트리밍을 위해 DSP를 내장한 SoC (System-on-Chip) 플랫폼 상에서 임베디드 블루투스 솔루션의 개발과 최적화에 대해 설명한다. 개발된 솔루션을 이식성을 고려해서 가상 운영체제 상에서 구현된 임베디드 블루투스 프로토콜 스택, 프로파일과 타겟 멀티미디어 SoC의 특성을 이용한 최적화 기법들을 포함한다. 수요 최적화 기법으로는 SoC 내의 스크래치 패드 메모리의 활용을 통한 메모리 접근 최소화, DSP 연산과 병렬 메모리 접근 명령을 이용한 코덱 구현, 무선 통신 환경을 고려한 동적 오디오 품질 조정 등이 있다. 실험 결과는 본 연구에서 제안한 최적화 기법을 적용한 임베디드 솔루션은 별도의 외부 메모리 없이 고품질 오디오 스트리밍을 지원할 수 있음을 보여준다. In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.

Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip

One of the difficult problems facing core-based system-on-chip (SoC) designs is test access. For testing the cores in an SoC, a special mechanism is required since they are not directly accessible via chip inputs and outputs. In this paper, we introduce a novel test access mechanism (TAM) based on time-division multiplexing (TDM). This so-called TDM-TAM is P1500 compatible and, in fact, uses a P1500 wrapper. The TAM advantages are its flexibility, scalability, and reconfigurability. Also this TAM could be very useful for testing multi-frequency cores in SoCs because, with TDM, the test data rate can be changed. The proposed TAM is compared with two other approaches: a serial threading approach analogous to the IEEE1149.1 standard (Serial TAM) and a packet-switching test network (called NIMA). A network processing unit is used as an SoC platform to compare the different TAMs. Results show that, in most cases, TDM is the most effective TAM in both test time and overhead area.

Debug support strategy for systems-on-chips with multiple processor cores

On-chip program and data tracing is now an essential part of any system level development platform for system-on-chip (SoC). Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interfaces to decouple the debug support from processor cores and other active data accessing units. The on-chip debug support infrastructure is also decoupled from each core's debug support and from the trace port or trace memory, using an additional interface. As a result, this decoupling of the debug support infrastructure provides freedom from a specific SoC platform. These interfaces are applied through a reference design modeled using VHDL that is based on a novel low overhead trace message framework. Compared with a leading implementation of a relevant standard, the reference design is 50 percent more compact while providing improvements in trace compression of 8.4 percent for program trace messages and almost 24 percent for data trace messages. This reference design is a multiple core solution that is compatible with most SoC architectures, including those based on emerging network-on-chip architectures.

Object Recognition System-on-Chip Using the Support Vector Machines

The first aim of this work is to propose the design of a system-on-chip (SoC) platform dedicated to digital image and signal processing, which is tuned to implement efficiently multiply-and-accumulate (MAC) vector/matrix operations. The second aim of this work is to implement a recent promising neural network method, namely, the support vector machine (SVM) used for real-time object recognition, in order to build a vision machine. With such a reconfigurable and programmable SoC platform, it is possible to implement any SVM function dedicated to any object recognition problem. The final aim is to obtain an automatic reconfiguration of the SoC platform, based on the results of the learning phase on an objects' database, which makes it possible to recognize practically any object without manual programming. Recognition can be of any kind that is from image to signal data. Such a system is a general-purpose automatic classifier. Many applications can be considered as a classification problem, but are usually treated specifically in order to optimize the cost of the implemented solution. The cost of our approach is more important than a dedicated one, but in a near future, hundreds of millions of gates will be common and affordable compared to the design cost. What we are proposing here is a general-purpose classification neural network implemented on a reconfigurable SoC platform. The first version presented here is limited in size and thus in object recognition performances, but can be easily upgraded according to technology improvements.

An Undergraduate System-on-Chip (SoC) Course for Computer Engineering Students

The authors have developed a senior-level undergraduate system-on-chip (SoC) course at San Jose State University, San Jose, CA, that emphasizes SoC design methods and hardware-software codesign techniques. The course uses a "real world" design project as the teaching vehicle and implements an SoC platform to control a five-axis robotic arm using Altera's state-of-the-art Excalibur chip. The Excalibur chip contains both ARM Corporation's embedded processor and a programmable logic device (PLD) array. The course goes through a complete hardware-software codesign flow from implementing custom hardware devices on a PLD to developing an embedded algorithm in a state-of-the-art design environment for a complete SoC solution. Students learn the Quartus II design environment by examining the sample design files in Altera's EXPA1 development kit and following the step-by-step instructions toward creating a simple embedded application. After this familiarization process, students define the architectural specifications of a memory-mapped servo controller, implement it in the Excalibur's PLD array, and interface this device with the ARM processor's internal bus to control each robotic arm servo. Functional regression tests and post-synthesis timing verification steps are applied to the servo controller following the implementation phase. Subsequently, students integrate the servo controller with the rest of the system and perform board-level functional verification tests to observe whether the robotic arm can move an object from a source to a destination point accurately. Students also develop an embedded algorithm, which translates user inputs in Cartesian coordinates into robotic arm movements in spherical coordinates during laboratory sessions.

Run-time support for heterogeneous multitasking on reconfigurable SoCs

In complex reconfigurable systems on chip (SoC), the dynamism of applications requires an efficient management of the platform. To allow run-time management of heterogeneous resources, operating systems (OS) and reconfigurable SoC platforms should be developed together. For run-time support of reconfigurable architectures, the OS must abstract the reconfigurable computing resources and provide an efficient communication layer. This paper presents our efforts to simultaneously develop the run-time support and the communication layer of reconfigurable SoCs. We show that networks-on-chip (NoC) are an ideal communication layer for dynamically reconfigurable SoCs, explain how our OS provides run-time support for dynamic task relocation and detail how hardware parts of the OS are integrated into the higher layers of the NoC. An implementation of the OS and of the dedicated communication layer on our reconfigurable architecture supports the concepts we describe.

Low-power system-on-chip architecture for wireless LANs

The authors present the architecture of a low-power system-on-chip (SoC) that implements baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. The design is based on the HIPERLAN/2 wireless LAN standard, but it also covers critical processing requirements of the IEEE 802.11a standard. The options, constraints and motivations for the taken design decisions are presented, and the followed design steps, starting from the system specifications up to the architecture definition and the system implementation, are explained. The system's functionality covers both mobile terminal and access point devices. A critical design task in such systems is the assignment of the target system's tasks on the different types of processing elements available. Processor cores, dedicated hardware as well as memory elements and advanced bus architectures are used in order to achieve the target implementation. The architecture is targeted for a low-power SoC platform, due to the fact that power consumption is a critical parameter in electronic portable system design where excess power dissipation can lead to expensive and less reliable systems. A system prototype has been developed on a FPGA-based platform (including microprocessor modules). This FPGA-based prototype is currently being migrated to a SoC, which requires that the treatment of important issues such as clock handling, synthesis, testability and debugging is addressed.

Bus encoding architecture for low-power implementation of an AMBA-based SoC platform

Advanced microcontroller bus architecture (AMBA) is rapidly becoming the de facto standard for new system-on-chip (SoC) designs. The bus protocol is complex, making any peripherals that can interface to it valuable intellectual property (IP). This paper presents a low-power bus encoding architecture which is able to deal with the complex advanced high- performance bus (AHB) protocol within AMBA, which involves multiple burst transfers. The architecture is targeted for a low-power SoC platform to be used in a miniaturised low power application area. The paper describes the SoC platform and the bus encoding architecture, and provides results with a design synthesised at 0.35 µm CMOS technology indicating up to 22% power saving.