System On A Programmable Chip Research Articles

An Approach to the State Explosion Problem: SOPC Case Study

The system on a programmable chip (SOPC) architecture is better than traditional central processing unit (CPU) + field-programmable gate array (FPGA) architecture. It forms an efficient coupling between processor software and programmable logic through an on-chip high-speed bus. The SOPC architecture is resource-rich and highly customizable. At the same time, it combines low power consumption and high performance, making it popular in the field of high reliability and other new industrial fields. The SOPC architecture system is complex and integrates multiple forms of intellectual property (IP). Because of this, the traditional dynamic test and the static test cannot meet the requirements for test depth. To solve the problem of verification depth, we should introduce formal verification. But there are some types of IP forms that formal tools cannot recognize. These include black box IP, encrypted IP, and netlist IP in the SOPC model. Also, the state space explosion caused by the huge scale of the SOPC model cannot be formally verified. In this paper, we propose a modeling method using SOPC architecture. The model solves the problem of formal tools not recognizing multi-form IPs. To compress the state space, we propose reducing SOPC variables and branch relationships based on verification properties. Then, we conduct a property verification experiment on the reduced SOPC model. The experiment result shows that the model can significantly reduce the verification time.

Evolutionary Optimization of Fuzzy Reinforcement Learning and Its Application to Time-Varying Tracking Control of Industrial Parallel Robotic Manipulators

This paper contributes to the development of evolutionary optimization of fuzzy reinforcement learning and its application to time-varying tracking control for industrial parallel robotic manipulators. An improved evolutionary social spider optimization (SSO) paradigm with Cauchy mutation is presented to address the optimal fuzzy reinforcement learning problem. The SSO swarm intelligence incorporated with the fuzzy Q-learning strategy, called SSOFQ, is applied to the time-varying tracking control of parallel robotic Stewart manipulators with six degrees of freedom (DOFs). Having the derived kinematics and dynamics of six-DOF Stewart platforms, the SSOFQ is employed to synthesize an intelligent real-time tracking control scheme. More importantly, a custom experimental Stewart platform is constructed using hardware/software codesign and the system-on-a- programmable chip (SoPC) technique. Finally, the simulations, experimental results and comparative works are provided to validate the efficacy and superiority of the presented SSOFQ control method.

Designing Photoelectric Sensor Module in Infrared Communication and Applying Wireless Sensor Network in Leakage Cable Detection

With technological advancement, Near-infrared (NIR) spectroscopy instruments have gradually entered people’s daily life and production with their unique performance. Therefore, it has a positive significance in researching NIR spectroscopy analysis technology. This work designs a refrigerating Lead Sulfide (PbS) NIR photoelectric sensor P2664-05 and its photoelectric signal conversion circuit. The converted voltage signal is used for subsequent circuit processing through the amplification and frequency selection circuit. The aim is to ensure the sensor’s corresponding detectable spectral wavelength, sensitivity, and signal-to-noise ratio are improved under low temperatures. To this end, the refrigeration current generation circuit is designed. The refrigerating temperature is set below −15 °C, and the refrigerating current is 500 mA. At the same time, it is necessary to monitor whether the sensor’s temperature state meets the system stability requirements during the refrigeration process. The designed sensor module is connected to the instrument system in the test, and the whiteboard without spectral absorption is scanned. The results show that the designed NIR sensor’s shortcomings in noise processing performance have been improved using a System on a Programmable Chip (SoPC) as a processor. An infrared communication node is designed using its built-in digital resources and TFDU infrared communication chip. The designed NIR sensor and communication node are added to the 485 bus to build a communication network. In leakage cable detection, the communication network has higher security, lower error rate, and lower power consumption.

A SEPIC-based three-port converter system using a mode-specific power flow management control for solar energy harvesting

The growing demand of renewable energy sources in the energy sector has a considerable impact on the development of stand-alone solar photovoltaic (PV) systems. Three-port converter (TPC) topologies are widely used as a gateway between solar PV, energy storage, and loads. This paper proposes a three-port converter with buck and boost operating modes. The topology is SEPIC-based rather than the conventional buck-boost or Cuk circuit, hence eliminates the inverting output and reduce the input current ripple. The series capacitor in a SEPIC converter endows the TPC with inherent protection against short-circuit output. The TPC has four modes of operation: Dual Output (DO) mode, Dual Input (DI) mode, Single Input Single Output-1 (SISO-1) mode and Single Input Single Output-2 (SISO-2) mode. The power flow management algorithm employs a mode-specific voltage regulation strategy that distributes the duty cycle for each switch via time-sharing control scheme. Small signal model of the TPC is developed in each operating mode and based on this, voltage controller parameters are derived. When the TPC changes modes, the algorithm modifies the controller parameters to the mode-specific values. The proposed system is implemented by utilising the FPGA Cyclone-III comprising the Nios-II processor core with necessary hardware intellectual property (IP) forming a System on a Programmable Chip (SoPC). The system is evaluated in real time using a 120W solar PV as the energy source and lead-acid battery as the storage.

An autonomous solar PV system using boost TPC for energy harvesting with mode-based power flow management control

Energy harvesting from environment provides a compelling alternative to battery-powered standalone systems. The rising use of green energy resources in energy sector has a substantial impact on the low voltage DC (LVDC) systems. Multiport converters make it easier to convert renewable energy for use in everyday situations. To ensure uninterruptible power supply, a non-isolated Three-Port Converter (TPC) acts as a gateway for renewable sources, energy storage, and loads. The paper describes a modified power flow management control for a standalone solar PV system using boost TPC with time sharing control and an added mode-based controller for voltage regulation. To operate the TPC effectively in Dual Output (DO), Dual Input (DI) and Single Input and Single Output (SISO) modes, localized controllers are used. The converter small signal model is developed for all operating modes and based on this, sampled data control theory is applied to design the digital controller for load regulation. When the TPC switches from one operating mode to another, the voltage regulation control sets the controller parameters for the appropriate mode. Also, to extend battery lifespan, the control algorithm includes a battery overcharge prevention mechanism. The proposed algorithm is realized in a System on a Programmable Chip (SoPC) using the Field Programmable Gate Array (FPGA) Cyclone-III and Nios-II as processor. The system is tested in real time with solar PV as the source of energy and a lead-acid battery as the storage.

The Effect of Multimedia Teaching Model of Music Course in Colleges and Universities Based on Classroom Audio Data Mining Technology

Objectives: With the rapid development of information technology, multimedia teaching mode carries a large amount of audio-visual information, quickly occupies the music classroom in Colleges and universities, and becomes the mainstream teaching mode of music teaching in Colleges and universities. Methods: Based on this, this study uses classroom audio data mining technology to analyze the effect of multimedia teaching mode of music courses in Colleges and universities. The method of audio data mining is analyzed in college music multimedia classroom. The advanced embedded SOPC system is used to decode the MP3 audio files played in music courses by combining software and hardware. The performance of the multimedia teaching system in college music courses is optimized. Results: The hardware resources are made use of the flexibility of SOPC (System-on-a-Programmable-Chip) system. Reasonable allocation achieves the optimal design of teaching mode. Finally, the superiority of the algorithm is verified by testing. The test results show that the decoding speed and efficiency of audio files can be significantly improved by combining hardware and software. Conclusion: At the same time, the system has greater flexibility and expandable space, which can effectively promote the multimedia teaching effect of music courses in Colleges and universities. The research in this paper is helpful to the flexible transformation of multimedia teaching mode of music courses in Colleges and universities, and provides an important reference for the popularization of multimedia and the wide use of data mining technology in music courses in Colleges and universities.

Gaussian Belief Propagation on a Field-Programmable Gate Array for Solving Linear Equation Systems

Solving Linear Equation System (LESs) is a common problem in numerous fields of science. Even though the problem is well studied and powerful solvers are available nowadays, solving LES is still a bottleneck in many numerical applications concerning computation time. This issue especially pertains to applications in mobile robotics constrained by real-time requirements, where on-top power consumption and weight play an important role. This paper provides a general framework to approximately solve large LESs by Gaussian Belief Propagation (GaBP), which is extremely suitable for parallelization and implementation in hardware on a Field-Programmable Gate Array (FPGA). We derive the simple update rules of the Message Passing Algorithm for GaBP and show how to implement the approach efficiently on a System on a Programmable Chip (SoPC). In particular, multiple dedicated co-processors take care of recurring computations in GaBP. Exploiting multiple Direct Memory Access (DMA) controllers in scatter-gather mode and available arithmetic logic slices for numerical calculations accelerate the algorithm. Presented evaluations demonstrate that the approach does not only provide an accurate approximative solution of the LES. It also outperforms traditional solvers with respect to computation time for certain LESs.

Research on Non-intrusive Residential Electric Load Identification System Based on SOPC

The high-precision identification of the non-intrusive residential electrical load is an essential technology to realize the intelligentization of the power grid. Due to its low input cost and easy maintenance, this technology has received much attention at home and abroad. In order to improve the accuracy of load identification, this paper proposes a non-intrusive residential electric load monitoring equipment based on system on a programmable chip (SOPC), which is focused on hardware system design, characteristic parameters optimizing and BP neural network algorithm optimization. The feasibility of the system was verified by experimental simulation and tests. The results of experiment show that the method used for hardware design can not only improve the speed of system and most closely match the actual running state of electrical appliances in testing circumstances, but it can also realize the function of load identification rapidly and accurately under the condition of the given residential electricity.

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4 × 4, 8 × 8, 16 × 16 and 32 × 32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64 × 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4 × 4 to 64 × 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@3840 × 2.160 for 4 × 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64 × 64 size.

Development of a new distributed hybrid seismic and electrical data acquisition station based on system-on-a-programmable-chip technology

Abstract. In the past few decades, with the continuous advancement of technology, seismic and electrical instruments have developed rapidly. However, complex and harsh exploration environments led to higher requirements and severe challenges for traditional geophysical exploration methods and instruments. Therefore, it is extremely urgent to develop new high-precision exploration instruments and data acquisition systems. In this study, a new distributed seismic and electrical hybrid acquisition station is developed using system-on-a-programmable-chip (SoPC) technology. The acquisition station hardware includes an analog board and a main control board. The analog board uses a signal conditioning circuit and a 24-bit analog-to-digital converter (ADS1271) to achieve high-precision data acquisition, while the main control board uses a low-power SoPC to enable high-speed stable data transmission. We designed the data transmission protocol for the acquisition station and developed independently an improved low-voltage differential signaling data transmission technology. What's more, a method to enhance the precision of synchronous acquisition was studied in depth. These key technologies, which were developed for the acquisition station, were integrated into the SoPC of the main control board. Test results indicate that the synchronization precision of the acquisition station is better than 200 ns, and the maximum low-power data transmission speed is 16 Mbps along a 55 m cable. The developed acquisition station has the advantages of low noise, large dynamic range, low power consumption, etc., and it can achieve high-precision hybrid acquisition of seismic and electrical data.

A Networked Multirobot CPS With Artificial Immune Fuzzy Optimization for Distributed Formation Control of Embedded Mobile Robots

This article presents a networked multirobot cyber-physical system (CPS) that employs artificial immune fuzzy optimization to achieve distributed formation control of embedded mobile robots. The artificial immune system (AIS) algorithm is combined with a fuzzy system to develop a hybrid optimization technique, called AIS-fuzzy. This metaheuristic is applied to designing the intelligent third cyber and fourth cognition levels in the networked multirobot CPS 5C structure of embedded robots to accomplish distributed formation control. The proposed CPS cyber and cognition levels with AIS-fuzzy paradigm incorporate with the first, second, and fifth levels by means of robotic sensors and actuators. System-on-a-programmable-chip (SoPC) methodology is adopted to present a pragmatic networked multirobot CPS in the field-programmable gate array chips. The presented SoPC-based AIS-fuzzy multirobot CPS features the seamless integration of computation, networking, and physical robotic processes. Experimental results are obtained, and comparative analyses are provided to illustrate the effectiveness and merits of the proposed multirobot CPS to perform distributed formation control of embedded mobile robots.

FPGA implementation of extended Kalman filter for SOC estimation of lithium‐ion battery in electric vehicle

AbstractA FPGA implementation for a model‐based state of charge (SOC) estimation is described in this paper. A Thevenin equivalent circuit model is designed for SOC estimation. The extended Kalman filter (EKF) is designed to complete the SOC estimation, and the error is within 1 % . The FPGA is chosen to achieve realtime SOC estimation. A fast matrix method is proposed to improve the calculation speed of the EKF in FPGA because the EKF algorithm requires many matrix operations. In addition, the embedded system based on the FPGA with a system on a programmable chip (SOPC) technique is built using the Qsys platform in Quartus II. Based on the embedded system, an online testing platform is established to monitor the terminal voltage and load current of the experimental battery in real time; experimental results show that the online SOC estimation is successful. The measurement results show that the FPGA embedded scheme of the EKF allows for successful implementation of the SOC estimation with accuracy and speed. The fast matrix method requires 0.00007 s to implement the SOC estimation and is four times faster than the conventional matrix method.

Hardware-Based Protection for Data Security at Run-Time on Embedded Systems

The security of embedded systems has attracted much attention as they are being used in more and more fields. The rapid growth and pervasive use of embedded systems make it easier for a sophisticated attacker to gain physical access to launch physical attacks on insecure off-chip memory and bus. This paper presents a novel hardware-based security mechanism to protect confidentiality and integrity of data, preventing the system data from being stolen or tampered by a malicious attacker. The proposed mechanism protects the confidentiality of data using advanced encryption standard (AES) stream encryption algorithm in parallel with the memory access process. This mechanism provides integrity protection for data by attaching integrity signatures generated using hash algorithm to data stored in external memory. The signature is verified when data is fetched into the chip. The security architecture has been tested and validated on the system on a programmable chip (SoPC) with OR1200(processor based on OpenRISC1000 architecture) processor. The experimental result shows that the proposed security mechanism ensures the integrity and confidentiality of system data, introducing low performance penalties.

The Design of IP Core for LCD Controller Based on SOPC

In this paper, it introduces the design and implementation of custom IP core for liquid crystal display (LCD) controller based on system on a programmable chip (SOPC) technology and Verilog hardware description language (HDL). The IP core can be put up as a general-purpose peripheral module to the Avalon Bus, communicating with the NIOS II through registers, and the underlying sequential logic for communicating with the external LCD liquid crystal module is automatically completed by the module. The driver does not need to care about the details of the underlying timing, it only needs to implement the read and write operations of the LCD data through register access, thus achieve the purpose of controlling the display content of the LCD. In addition to reducing the complexity of driver development, the design can also take full advantage of the parallel operation of hardware logic to improve the execution efficiency of the entire system and the throughput of processing tasks, especially in some occasions where high-speed image real-time processing is required. Simulations and experiments show that the IP core for LCD controller has good stability, versatility and compatibility.

Remote System Update for System on Programmable Chip Based on Controller Area Network

In some application domains, using a download cable to update the system on a programmable chip (SoPC) is infeasible, which reduces the maintainability and flexibility of the system. Hence the remote system update (RSU) scheme is being studied. In this scheme, the serial configuration (EPCS) device involves a factory mode configuration image, which acts as the baseline, and an application mode configuration image, which is used for some specific functions. Specifically, a new application mode image is delivered through the controller area network (CAN) with the improved application layer protocol. Besides, the data flow and data check for transmitting a new image are constructed to combine the transmission reliability with efficiency. The boot sequence copying hardware configuration code and software configuration code is analyzed, and the advanced boot loader is carried out to specify boot address of the application mode image manually. Experiments have demonstrated the feasibility of updating and running a new application mode image, as well as rolling back into the factory mode image when no application mode image is available. This scheme applies a single CAN bus, which makes the system easy to construct and suitable for the field distributed control system.

Design and implementation of a pulse wave generator based on Windkessel model using field programmable gate array technology

Abstract Purpose Pulse wave contains plenty of physiological and pathological information of cardiovascular system. There have been many commercial products that can analyze pulse wave signals for the quantification of cardiovascular functions. However, their performance often varies from case to case. It is thus necessary to generate typical pulse waveforms in order to quantitatively evaluate these commercial products. Methods A pulse wave generator based on the Windkessel model is designed and implemented in this study because Windkessel model can describe the general features of a pulse wave with physiologically interpretable parameters that can be easily set by users. The numerical solutions are obtained by using the Runge-Kutta method. Results The features of this work include: (1) the critical parameters are flexible to be modulated so that different pulse waveforms representing different states of the cardiovascular system could be simulated; (2) it is possible to add different types of noises with varying signal-to-noise ratios; (3) the software is designed under the System-on-a-Programmable-Chip (SoPC) developing flow; (4) the platform is implemented on Field Programmable Gate Array (FPGA) for efficiency, portability and scalability. Conclusion and significance The pulse waves generated by the designed generator are quite similar to these measured in clinic. The new pulse wave generator is useful to test and evaluate various pulse wave analysis devices. It is also useful for the training of hospital personnel and young students.

FPGA-Based HD Camera System for the Micropositioning of Biomedical Micro-Objects Using a Contactless Micro-Conveyor

With recent advancements, micro-object contactless conveyers are becoming an essential part of the biomedical sector. They help avoid any infection and damage that can occur due to external contact. In this context, a smart micro-conveyor is devised. It is a Field Programmable Gate Array (FPGA)-based system that employs a smart surface for conveyance along with an OmniVision complementary metal-oxide-semiconductor (CMOS) HD camera for micro-object position detection and tracking. A specific FPGA-based hardware design and VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) implementation are realized. It is done without employing any Nios processor or System on a Programmable Chip (SOPC) builder based Central Processing Unit (CPU) core. It keeps the system efficient in terms of resource utilization and power consumption. The micro-object positioning status is captured with an embedded FPGA-based camera driver and it is communicated to the Image Processing, Decision Making and Command (IPDC) module. The IPDC is programmed in C++ and can run on a Personal Computer (PC) or on any appropriate embedded system. The IPDC decisions are sent back to the FPGA, which pilots the smart surface accordingly. In this way, an automated closed-loop system is employed to convey the micro-object towards a desired location. The devised system architecture and implementation principle is described. Its functionality is also verified. Results have confirmed the proper functionality of the developed system, along with its outperformance compared to other solutions.

An energy-efficient system on a programmable chip platform for cloud applications

Performance analysis of master-slave based reconfigurable architecture and standalone SOPC based reconfigurable architecture using an analytical model.A massive-sessions optimized TCP/IP offload engine that supports up to 100K TCP sessions under 10Gbps line rate.An online dynamic scheduling method that can reconfigure or power off FPGA nodes according to workload variance to reduce the runtime energy consumption.Prototype of a reconfigurable cluster system based on standalone SOPC to provide cloud services, achieving up to 38X speed up in performance and 418X improvement in energy efficiency compared to the software based cloud systems. Traditional cloud service providers build large data-centers with a huge number of connected commodity computers to meet the ever-growing demand on performance. However, the growth potential of these data-centers is limited by their corresponding energy consumption and thermal issues. Energy efficiency becomes a key issue of building large-scale cloud computing centers. To solve this issue, we propose a standalone SOPC (System on a Programmable Chip) based platform for cloud applications. We improve the energy efficiency for cloud computing platforms with two techniques. First, we propose a massive-sessions optimized TCP/IP hardware stack using a macro-pipeline architecture. It enables the hardware acceleration of pipelining execution of network packet offloading and application level data processing. This achieves higher energy efficiency while maintaining peak performance. Second, we propose a online dynamic scheduling strategy. It can reconfigure or shut down FPGA nodes according to workload variance to reduce the runtime energy consumption in a standalone SOPC based reconfigurable cluster system. Two case studies including a webserver application and a cloud based ECG (electrocardiogram) classification application are developed to validate the effectiveness of the proposed platform. Evaluation results show that our SOPC based cloud computing platform can achieve up to 418X improvement in terms of energy efficiency over commercial cloud systems.

A Hardware/Software Co-design of High Efficiency AAC Audio Decoder

This paper presents an implementation of hardware/software co-design for high efficiency advanced-audio-coding (HE-AAC) audio decoder. The decoder system is partitioned into software and hardware part throughout the computation analysis. In our design strategy, the bitstream parser and lower complexity part are performed by software solution, and the higher complexity part is computed by hardware solution. As in the dedicated hardware, four units are developed to cope with IMDCT, analysis quadrature mirror filterbank (AQMF), HF generator and envelope adjuster and synthesis quadrature mirror filterbank (SQMF). To support the various types of transformation-based functions in HE-AAC decoding, we manipulate it based on the decomposition of common radix-2 FFT method. The hardware part is designed as an intellectual property (IP) by TSMC 90 nm library. As a cost-effective design, it consumes about 150 K gates and executes at a very low operation frequency with 1.75 MHz. The power consumption is only 7.69 mW with some low power design considerations. Moreover we construct the overall system including the wrapper design and embedded platform as a system on a programmable chip (SOPC) platform. With this design approach, over 91.26 % processor-based loading can be saved and substituted by this hardware IP.