System On A Programmable Chip Research Articles

Design of a shift-and-add based hardware accelerator for color space conversion

In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid the inefficiency of CSC circuit architecture due to massive floating-point multiplication operations in the conversion formulae, a GA-based evolutionary technique is used to realize the fast multiplierless CSC hardware architecture. Meanwhile, a pipeline design method is further applied to enhance the maximum operating frequency in circuit design. As compared to the commonly used floating-point based CSC architecture, the pipelined CSC HA in this paper has excellent advantages of low-complexity and high speed. After the mechanism is integrated into a system-on-a-programmable-chip (SOPC), the maximum operating frequency reached 168.12 MHz. That is, in every 0.11 s, the color space conversion can process a 512 × 512 image. This excellent result is practical to the fast development of different kind of image/video processing systems.

Realization of a Motion Control System for Wafer-Handling Robot Using SoPC Technology

The novel FPGA (Field Programmable Gate Arrays) can embed a processor to be an SoPC (System-on-a-Programmable-Chip) environment which allows user to design the applications by mixing hardware and software. Therefore, a motion control system of wafer-handling robot based on the SoPC technology is presented in this paper. In FPGA, it is consists of two modules. The first module is Nios II processor which is used to realize the motion trajectory planning and three-axis position/speed controllers by software. The program developed in Nios II processor uses C language. The second module is presented to implement three-axis current vector controllers by hardware, and VHDL (VHSIC Hardware Description Language) is applied to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as three current vector controllers, three position/speed controller and one trajectory planning are all can implemented by a single FPGA chip. Finally, an experimental system constructed by an FPGA experimental board, one three-DOF wafer-handling robot, and three inverters is set up to demonstrate the correctness and effectiveness of the proposed SoPC-based motion control system of wafer-handling robot.

Intelligent Motion Control for Four-Wheeled Holonomic Mobile Robots Using FPGA-Based Artificial Immune System Algorithm

This paper presents an intelligent motion controller for four-wheeled holonomic mobile robots with four driving omnidirectional wheels equally spaced at 90 degrees from one another by using field-programmable gate array (FPGA)-based artificial immune system (AIS) algorithm. Both the nature-inspired AIS computational approach and motion controller are implemented in one FPGA chip to address the optimal control problem of real-world mobile robotics application. The proposed FPGA-based AIS method takes the advantages of artificial intelligence and FPGA technology by using system-on-a-programmable chip (SoPC) methodology. Experimental results are conducted to show the effectiveness and merit of the proposed FPGA-based AIS intelligent motion controller for four-wheeled omnidirectional mobile robots. This FPGA-based AIS autotuning intelligent controller outperforms the conventional nonoptimal controllers, the genetic algorithm (GA) controller, and the particle swarm optimization (PSO) controller.

Design of the Nios II System for the Playing of Wave Files on an Altera DE2 Board

The motivation behind this study is the impact made on today's social media by music players, which include features like portability, size and equalizer functionality for the best possible sound output quality. The objective of this study was to develop a system that reads the wave files present on the Secure Data (SD) card, adjust the equalizer settings incorporated on it, and play them on the speaker with the best possible quality sound output. This was done with the help of the SD card slot provided on the DE2 board, and its implementation on the board using Altera's SoPC (System-on- a-Programmable-Chip) Builder in the Altera Quartus 9.1 environment. Nios II is a 32-bit soft-core embedded processor architecture designed specifically for the Altera family of FPGAs. Programming of the Nios II processor is done using the Nios II 9.1 IDE tool. An extension of this work could include incorporation of video—along with the audio on the DE2 board since there is a VGA slot included on the board features and the movement of the wave files on the SD card with the help of the keys present on the DE2 board .

Application of DFG Model on SOPC Technology

HW/SW (hardware/software) co-design method based on analysis and optimization of DFG (data flow graphic) model is introduced for SOPC (System on a Programmable Chip) used for digital instrument design in this paper. The method is based on the DFG model of the digital signal process algorithm and implemented with SOPC technology. The DFG model could help designer to divide the function into hardware and software respectively, therefore, the optimizing analysis at system level and circuit level of a SOPC used for portable logic analyzer shows that the DFG model is very useful for not only optimizing architecture and power consumption, but also HW/SW co-design.

Research on Internet of Things Based on SOPC

An Internet of things system using Cyclone EP2C8 FPGA chip of Altera is designed and researched in this paper, which integrated NiosII soft-core processor, memory, functional interfaces with SOPC (system on a programmable chip) technology. The μC/OS-II embedded operating system is transplanted here to realize the network communication through driving the network chip. Simultaneously, the message stored in card can be correctly identified, recorded, added up by RFID technology, and sent to internet according to the requirement of communication. Thus, the internet of things function is realized.

Field programmable gate array/system on a programmable chip-based implementation of model predictive controller

To improve the on-line computational performance of model predictive control (MPC) for fast systems and/or embedded systems, this study proposes a novel scheme for the MPC controller implementation based on field programmable gate array (FPGA) and system on a programmable chip (SOPC) technology. A Nios II processor clocked at 150 MHz is embedded into the FPGA chip. A C/C++ model of the MPC algorithm which is run in the Nios II processor is created. The dual method is adopted to solve the quadratic programming (QP) problem. Based on FPGA and dSPACE®, a rapid prototyping platform is introduced to test and verify the function and computational performance of the MPC controller. Real-time simulation results of controlling a throttle model show that a reasonable size of constrained MPC controller can be implemented on the used RCIII FPGA board.

Hardware Software Co-Design for JPEG Encoder Test Bench

This paper presents a hardware/software (HW/SW) co-design approach using System On a Programmable Chip (SOPC) technique to achieve Joint Photographic Experts Group (JPEG) algorithm. It firstly introduces JPEG image compression technology and the system architecture. Then the hardware/software design process of JPEG encoder test bench is introduced. It focuses on using the characteristics of Field-Programmable Gate Array (FPGA) structure to achieve JPEG algorithm including the improved Discrete Cosine Transform (DCT), and Nios II embedded processor of customizable characteristics, translating image acquisition, JPEG image compression and Thin Film Transistor Liquid Crystal Display (TFT-LCD) controller into user-defined modules according to Altera Avalon bus requirements with the SOPC Builder, where the user-defined module can be added to the system under the control of soft-core Nios II Embedded. Finally, the whole system is verified on a single FPGA chip. The experimental results shows the advantages of JPEG algorithm as a FPGA hardware module includes low power consumption, high image quality, low production costs and stable performance. There’s a very great practical significance to reduce costs and improve image processing speed.

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

Block matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5MHz frequency clock and uses only 28kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system.

DESIGNING A SOPC FOR FACE RECOGNITION USING WMPCA ALGORITHM

A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using weighted modular principal component analysis (WMPCA) and its system-on-programmable-chip (SoPC) implementation are discussed.

A Grey Synthesis Approach to Efficient Architecture Design for Temporal Difference Learning

Temporal difference (TD) constitutes a class of methods for learning predictions in multistep prediction problems. The most important application of these methods is to temporal credit assignment in reinforcement learning. Although these TD procedures work in theory and in principle, its success is contingent on proper selection of parametric values. As well, its learning is majorly based on repeated exposures, which may not always be practical or feasible. This paper examines the issues of the efficient and general implementation of TD for hardware implementation of reinforcement learning algorithms by synthesizing the series of discounted sum of rewards along time. The proposed algorithm eliminates all step size parameters and improves data efficiency based on a synthetic approach of Grey theory. This paper also presents the stability of the proposed algorithm from the viewpoint of Grey theory. The algorithm along with a critic-actor reinforcement learning model is implemented in a System-on-a-Programmable-Chip (SOPC) board. In addition to comparing with the renowned model, adaptive heuristic critic (AHC), the results of experiments demonstrate that the proposed control mechanism can learn to control a system with very little a priori knowledge. Meanwhile, the effect of uncertainty in interactions between the system and the environment can be relaxed to some extent in the learning process of the proposed reinforcement learning agent.

Velocity control realisation for a self-balancing transporter

This study proposes the motion control design of a real self-balancing transporter (SBT) which is fabricated in the laboratory. Based on the system-on-a-programmable-chip (SoPC) developmental architecture, two controls are implemented to achieve the objectives of balanced standing and moving with a constant velocity for the SBT. Based on the Takagi–Sugeno (T–S) fuzzy model of the SBT, the parallel distributed compensation (PDC) controller is employed to achieve the mentioned controls. Then an extra Mamdani If–Then fuzzy rule base (FRB) is built to cooperate with the PDC control such that the SBT not only can stand with balance, but can also move forward with a desired constant velocity ‘quickly’. The maximum emphasis is that there is a novel idea in the design of the If–Then FRB which is the relationship between the moving velocity error and the desired inclination angle of the SBT. Owing to the aids of the extra If–Then FRB, the time of the controlled response to reach the desired state is obviously shortened. This is the significant contribution of the study. Finally, both the fuzzy PDC and the If–Then FRB are realised in the SoPC platform for the real SBT. The performance and merit of the proposed control scheme is exemplified by conducting computer simulations and practical experiments.

A FPGA-Based Motion Control IC for X-Y Table

The new generation of Field Programmable Gate Array (FPGA) technology enables to embed a processor to construct a System on a Programmable Chip( SoPC). A stepper motion control IC for X-Y table using SoPC technology is proposed in this thesis. The proposed motion control IC contains two modules. One module performs the functions of schedule and logic control. Due to the need of complicated control algorithm, it is implemented by software using Nios II embedded processor. The other module performs the functions of interpolation, acceleration and deceleration. Due to the need of high performance, this module is implemented by Programmable Logic Device (PLD) in FPGA. The use of SoPC technology can make the motion control IC of X-Y table more compact, high performance and low cost .

Design and Implementation of BLDCM Driver Based on SOPC

The Brushless Direct Current Motor (BLDCM) has been researched by many scholars because of its simple structure, high power density, high reliability and easy control. In this paper, a driver based on the system on a programmable chip (SOPC) is designed to implement adjustable subdivision. For SPWM, SVPWM frequency conversion control Direct Digital Synthesizer(DDS) is introduced, DDS Intellectual Property (IP) core is designed for motor control of frequency conversion. This driving system can solve the high subdivision problem, increase the driving torque and angle resolution, and smooth the motor angle. Employing the bottom-top design method, the circuit was described by the VHDL language, synthesized by integrated environment, and simulated by Modelsim in both behavior level and gate level through the PLI interface. According to experiment’s result, this driver has the advantages of easy debugging, high anti-interference ability, larger driving power, low volume and low cost in large scale production.

Design and Implementation of Fuzzy Control on a Two-Wheel Inverted Pendulum

This paper introduces the design and implementation of a two-wheel inverted pendulum (TWIP) system with a fuzzy control scheme and the system-on-a-programmable-chip (SoPC) technology. The control scheme includes three kinds of fuzzy controls which are the fuzzy balanced standing control (FBSC), the fuzzy traveling and position control (FTPC), and the fuzzy yaw steering control (FYSC). Based on the Takagi-Sugeno fuzzy model of the TWIP, the FBSC is a structure of a parallel distributed compensator solved by the linear matrix inequality approach. Based on the motion characteristic of the TWIP, the FTPC and the FYSC are designed with Mamdani architecture if-then rules. Furthermore, the fuzzy control scheme for the real TWIP is implemented into an SoPC development board with an embedded reduced-instruction-set-computer soft-core processor and user intellectual property modules. Both the computer simulations and practical experiments demonstrate the effectiveness of the proposed control scheme.

Image acquisition and VGA display system based on FPGA

Concerning the drawbacks of traditional PCI frame grabber,using Altera's DE2 development platform,image acquisition and VGA display system of programmable logic chip based on Field-Programmable Gate Array(FPGA) were designed.This system used the programmable logic chip FPGA which was in-built into soft-core NiosⅡ as the controller.The FPGA has image sensor,digital memory,video D/A converter and VGA display interface as its accessories.System used System On a Programmable Chip(SOPC) technology to obtain control and coding over FPGA and its accessories and eventually to acquire,process and display the real-time images.The design results prove that,the electronic system based on SOPC technique is flexible and efficient in terms of designing,ported strong,easy to achieve high-speed data acquisition,and it has high compatibility.

FPGA-Based Parallel DNA Algorithm for Optimal Configurations of an Omnidirectional Mobile Service Robot Performing Fire Extinguishment

This paper presents a coarse-grain parallel deoxyribonucleic acid (PDNA) algorithm for optimal configurations of an omnidirectional mobile robot with a five-link robotic arm. This efficient coarse-grain PDNA is proposed to search for the global optimum of the redundant inverse kinematics problem with minimal movement, thereby showing better population diversity and avoiding premature convergence. Moreover, the pipelined hardware implementation, hardware/software co-design, and System-on-a-Programmable-Chip (SoPC) technology on a field-programmable gate array (FPGA) chip are employed to realize the proposed PDNA in order to significantly shorten its processing time. Simulations and experimental results are conducted to illustrate the merit and superiority of the proposed FPGA-based PDNA algorithm in comparison with conventional genetic algorithms (GAs) for omnidirectional mobile robot performing fire extinguishment.

The Design Of Image Processing System Based On SOPC And OV7670

With the development of embedded technology, digital image processing technology is widely used in the field of artificial intelligence, intelligent transportation, medical equipment, and how to achieve real-time digital image acquisition, storage and process is a key technology. This paper describes a programmable system on chip SOPC (System On a Programmable Chip) and OV7670 image sensor, using the FIFO and SDRAM under the control of the DMA to directly data-transfer, to achieve high-speed digital image capture, storage, edge detection processing.The design greatly increase the speed of the image date collectiion and storage and is better than the same type of the design especially the anti-noise ability and the effectiveness of the digital image processing

Matrix Converter Protection and Computational Capabilities Based on a System on Chip Design With an FPGA

The matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. Traditionally, the MC has been controlled by means of a DSP, together with a field-programmable gate array (FPGA). The sole aim of the latter is to perform the safe commutation of the converter. This involves a waste of resources, as the excellent features of the FPGA are infrautilized by the control system. This paper deals with the implementation of the double-sided space vector modulation (DS SVM), commutation, reference-frame changes, and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. The designed cores are technology-independent descriptions, which means that the developed design can be used in the FPGAs of any manufacturer. Moreover, the proposed design, which has been validated experimentally, has obviated the need to use a DSP. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based system on a programmable chip (SoPC) has been designed. Due to the computational capacity of the developed cores, processing time is reduced to the order of nanoseconds. This allows a response in real time and very high modulation frequencies can be attained. Moreover, these cores operate independently, and simultaneously, therefore obviating the need for sequential control and its resulting latencies and leading to an increase in the safety of the MC.

Design of Signal Processing System for Doppler Speed Radar Based on SOPC

Doppler speed radar is a high precision velocity measuring instrument based on Doppler Effect, which has widely applications in measuring moving target’s velocity. In this paper, a novel design of Doppler signal processing system was presented to perform projectile’s speed measurement tasks. The system architecture is based on an Altera Cyclone II chip and designed as a System-on-a-Programmable-Chip (SOPC) with the help of an embedded Nios II software processor. And the SOPC system integrates CPU, memory, I/O interface and some other reconfigured modules required in system. According to the proposed scheme, the peripheral circuits were designed in this system, such as signal condition, A/D conversion and auto gain control (AGC) circuit. We also proposed to use spectral analysis method based on windowed FFT to deal with the measured target’s Doppler signal. Further, the signal source of simulating targets was used to testify the system feasibility. In addition, future work can include the further study on frequency estimation algorithms or comparisons of the proposed architecture with traditional design.