System-level Dynamic Power Management Research Articles

Dynamic Network State Learning Model for Mobility Based WMSN Routing Protocol

The rising demand of wireless multimedia sensor networks (WMSNs) has motivated academia-industries to develop energy efficient, Quality of Service (QoS) and delay sensitive communication systems to meet major real-world demands like multimedia broadcast, security and surveillance systems, intelligent transport system, etc. Typically, energy efficiency, QoS and delay sensitive transmission are the inevitable requirements of WMSNs. Majority of the existing approaches either use physical layer or system level schemes that individually can’t assure optimal transmission decision to meet the demand. The cumulative efficiency of physical layer power control, adaptive modulation and coding and system level dynamic power management (DPM) are found significant to achieve these demands. With this motivation, in this paper a unified model is derived using enhanced reinforcement learning and stochastic optimization method. Exploiting physical as well as system level network state information, our proposed dynamic network state learning model (NSLM) applies stochastic optimization to learn network state-activity that derives an optimal DPM policy and PHY switching scheduling. NSLM applies known as well as unknown network state variables to derive transmission and PHY switching policy, where it considers DPM as constrained Markov decision process (MDP) problem. Here,the use of Hidden Markov Model and Lagrangian relaxation has made NSLM convergence swift that assures delay-sensitive, QoS enriched, and bandwidth and energy efficient transmission for WMSN under uncertain network conditions. Our proposed NSLM DPM model has outperformed traditional Q-Learning based DPM in terms of buffer cost, holding cost, overflow, energy consumption and bandwidth utilization.

Duplication‐controlled static energy‐efficient scheduling on multiprocessor computing system

SummaryEnergy‐efficient scheduling is a step towards meeting green computing requirements. The work in this direction mainly aims at reducing dynamic energy consumption that includes clock gating, cache subbanking, and dynamic voltage and frequency scaling of underlying processors. However, the emergence of fast and compact transistor sizes has exponentially added onto the processor static power consumption, which has not been paid much attention. This article proposes a duplication‐controlled static energy‐efficient scheduling (C‐SEED) algorithm for scheduling precedence constrained applications on parallel computing systems. The C‐SEED algorithm couples adaptive threshold‐based duplication with system level dynamic power management technique to achieve its objectives. Dynamic power management works by selectively putting the energy‐consuming resources to efficient low‐power states for idle times to reduce energy consumption. Efficacy of the proposed algorithm is analyzed and compared against other relevant works on the basis of makespan and total energy (dynamic + static + communication) consumption. The extensive simulation results carried over large set of random and regular task graphs show that the proposed C‐SEED algorithm has potential to reduce energy consumption as well as makespan.

A survey of design techniques for system-level dynamic power management

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.