System-level Architecture Exploration Research Articles

A Top-Down Constraint-Driven Methodology for Smart System Design

Smart Systems collate leading technologies and solutions for the design of new generation embedded and cyber-physical systems. They can be applied to a broad range of application domains, from everyday life to mission and safety critical tasks, and achieve a wide set of functionality using diverging architectures. Smart system design needs to be achieved in a real multi-domain environment, where analog, digital, mixed-signal, and now even MEMS sub-systems tightly interact. With a traditional approach, these different units are designed separately, and finally merged at the electronic system level. However, given the increasing integration and interactions among components of different nature, methodologies enabling effective system-level architectural exploration are becoming more and more significant. Starting from a detailed analysis and classification of state-of-the-art use scenarios, and based on a review of the existing approaches, we present a top-down constraint-driven methodology for the design of new generation smart systems. It enables partitioning and propagation of high-level application-driven requisites towards low-level units in the design flow. The methodology reviews fundamental and cross-sectional system-level design aspects applied to the definition of an example case, to identify sub-system requirements towards the specifications of the electrical features of each internal unit.

Phase noise performance of fully differential sub-harmonic injection-locked PLL

A fully differential sub-harmonic injection-locked phase-locked loop (PLL) that achieves improved levels of phase noise performance through the incorporation of injection locking and fully differential architecture is presented. Details concerning the design of each building block are given and the corresponding simulation results are presented. The system level architecture exploration is introduced together with the phase noise analysis. A physical implementation of the proposed design using a standard 0.5 µm SiGe BiCMOS process is also presented as a case study in order to prove the functionality as well as the overall performance. Phase noise improvement is 20 dB at 1 kHz when a sub-harmonic of the free-running oscillation frequency at 2.5 GHz with a −15 dBm power level is injected.

Quality-driven model-based architecture synthesis for real-time embedded SoCs

The recent spectacular progress in modern microelectronics created a big stimulus towards development of embedded systems. Unfortunately, it also introduced unusual complexity which results in many serious issues that cannot be resolved without new more adequate development methods and electronic design automation tools for the system-level design. This paper discusses the problem of an efficient model-based multi-objective optimal architecture synthesis for complex hard real-time embedded systems, when using as an example a system-level architecture exploration and synthesis method that we developed.

Integrated modelling and generation of a reconfigurable network-on-chip

While a communication network is a critical component for an efficient system-on-chip multiprocessor, there are few approaches available to help with system-level architectural exploration of such a specialised interconnection network. This paper presents an integrated modelling, simulation and implementation tool. The network architecture can be co-simulated with embedded-software to obtain cycle-accurate performance metrics. This allows an energy and performance tuning of the NOC. Next it can be converted into VHDL for implementation. We discuss our approach by designing a flexible network-on-chip and present implementation results. The performance of our automatically generated network is comparable with a reference design directly developed in HDL.

A new approach for system-level architecture exploration

In this paper, we present a new design-space exploration approach which we call the symbolic program approach. The symbolic program approach is based on both the trace driven approach and the control data flow graph approach. As expected, the trajectory of the symbolic program approach appears somewhere in-between the two extremes mentioned above. Thus, it leads to the shorter simulation time while it can still give fairly accurate performance numbers. Moreover, it produces results that can be readily taken as input for further design. Keywords: System-level, design-space exploration traces, CDFG, symbolic programs.