System Design Flow Research Articles

Multilevel testability analysis and solutions for integrated Bluetooth transceivers

As use of wireless communications rises and profit margins shrink, low-cost solutions are becoming increasingly important. Incorporating test design and DFT into the system design flow is essential to achieving such solutions. This case study analyzes test requirements, implications, and test cost for low-cost Bluetooth systems, which enable communication among several electronic components.

Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. However, the major disadvantage is its relatively slow computational speed. For applications that require forward rotation (or vector rotation) only, we propose a new scheme, the modified vector rotational CORDIC (MVR-CORDIC) algorithm, to improve the speed performance of CORDIC algorithm. The basic idea of the proposed scheme is to reduce the iteration number directly while maintaining the SQNR performance. This can be achieved by modifying the basic microrotation procedure of CORDIC algorithm. Meanwhile, three searching algorithms are suggested to find the corresponding directional and rotational sequences so as to obtain the best SQNR performance. Three SQNR performance refinement schemes are also suggested in this paper. Namely, the selective prerotation scheme, selective scaling scheme, and iteration-tradeoff scheme. They can reduce and balance the quantization errors encountered in both microrotation and scaling phases so as to further improve the overall SQNR performance. Then, by combining these three refinement schemes, we provide a systematic design flow as well as the optimization procedure in the application of MVR-CORDIC algorithm. Finally, we present two VLSI architectures for the MVR-CORDIC algorithm. It shows that by using the proposed MVR-CORDIC algorithm, we can save 50% execution time in the iterative CORDIC structure, or 50% hardware complexity in the parallel CORDIC structure compared with the conventional CORDIC scheme.

A timing-driven design and validation methodology for embedded real-time systems

We address the problem of timing constraint derivation and validation for reactive and real-time embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system first to derive the timing constraints on the system's internal behavior and then use them to derive and validate the timing constraints on the system's external behavior. Our solution consists of the following contributions: a generalized task graph model, a comprehensive classification of timing constraints, algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, a codesign methodology that combines the model and the algorithms, and the implementation of this methodology in a tool called RADHA-RATAN. The main advantages of our solution are that it simplifies the problem of ensuring timing correctness of the system by reducing the complexity of the problem from system level to task level, and that it makes the codesign methodology timing-driven in that our solution makes it possible to maintain a handle on the system's timing correctness from very early stages in the system's design flow.

Introducing core-based system design

In recent years cores have captured the imagination of designers who understand the potential of using these cells like integrated circuits on a PC board in building on-chip systems. With a rich cell library of predesigned, preverified circuit blocks, cores provide an attractive means to import technology to a system integrator and differentiate products by leveraging intellectual property advantages. Most importantly, core use shortens the time to market for new system designs through design reuse. Practical implementation of this design scenario, however, is fraught with unresolved issues: design methods for building single-chip systems, challenges in test and sign-off for these systems, and intellectual property licensing, protection, and liability. Here, we examine the evolving design flow for microelectronic systems, the market for core cells, and the challenges in using core cells for design, integration, assembly, and test of onchip systems.

A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the minimized method (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 /spl mu/ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude.

Frictional and Thermal Behaviors of Sliding-Rolling Concentrated Contacts

Sliding-rolling disk scuffing tests were conducted over a wide range of sliding and sum velocities, using a straight mineral oil and three aviation gas turbine synthetic oils in combination with two carburized steels and a nitrided steel. Geometrically-similar disks of two different sizes were tested in two different disk testers of nearly similar designs. In addition to disk size and metallurgy, the surface treatment, surface texture, and surface roughness of the disks were also varied. The investigation further covered variations in the oil supply configuration and flow rate. It is shown that the disk friction coefficient is dependent not only on the oil-metal combination, but also on the disk surface treatment and topography as well as the operating conditions. The quasi-steady disk surface temperature and the mean conjunction-inlet oil temperature are shown to be strongly influenced by the frictional power loss at the contact, but not by the specific makeup of the frictional power loss. They are also influenced by the heat transfer from the disks, mainly by convection to the oil and conduction through the shafts, which are dependent on system design and oil flow rate.

Screens for screen printing of electronic circuits

This paper proposes a new quantitative and systematic design methodology for high-speed interpolation/ averaging ADCs. The methodology consists of a new mathematical BW/gain model derived from the pre-amps arrays static model and new small-signal model, a new offset modeling mechanism that can accurately estimate and help to reduce the offset, and hence a new systematic design flow. The methodology enables a quantitative and systematic analysis, conducts iterative and accurate calculation realized in MATLAB, and finally leads to an optimized ADC design that reaches a guaranteed optimum full-chip performance with given specs (i.e., resolution, speed, input range, power, input CM, etc.). The methodology shows significant advantage over the traditional trial-and-error ADC design approach with respect to performance and design efficiency, and is much more reliable in nanometer technologies. The proposed methodology was fully validated in silicon: a 4-bit 5GSps interpolation/averaging ADC is fabricated in a 65 nm CMOS technology and the measurement results show that our ADC has indeed achieved an outstanding and comparable overall performance compared to reported state-of-the art ADCs.