System Clock Rate Research Articles

Frequency-multiplexed entanglement for continuous-variable quantum key distribution

Quantum key distribution with continuous variables already uses advantageous high-speed single-mode homodyne detection with low electronic noise at room temperature. Together with continuous-variable information encoding to nonclassical states, the distance for secure key transmission through lossy channels can approach 300 km in current optical fibers. Such protocols tolerate higher channel noise and also limited data processing efficiency compared to coherent-state protocols. The secret key rate can be further increased by increasing the system clock rates, and, further, by a suitable frequency-mode-multiplexing of optical transmission channels. However, the multiplexed modes couple together in the source or any other part of the protocol. Therefore, multiplexed communication will experience cross talk and the gain can be minuscule. Advantageously, homodyne detectors allow solving this cross-talk problem by proper data processing. It is a potential advantage over protocols with single-photon detectors, which do not enable similar data processing techniques. We demonstrate the positive outcome of this methodology on the experimentally characterized frequency-multiplexed entangled source of femtosecond optical pulses with natural cross talk between eight entangled pairs of modes. As the main result, we predict the almost 15-fold higher secret key rate. This experimental test and analysis of frequency-multiplexed entanglement source open the way for the field implementation of high-capacity quantum key distribution with continuous variables.

Applicability of Squeezed- and Coherent-State Continuous-Variable Quantum Key Distribution over Satellite Links.

We address the applicability of quantum key distribution with continuous-variable coherent and squeezed states over long-distance satellite-based links, considering low Earth orbits and taking into account strong varying channel attenuation, atmospheric turbulence and finite data ensemble size effects. We obtain tight security bounds on the untrusted excess noise on the channel output, which suggest that substantial efforts aimed at setup stabilization and reduction of noise and loss are required, or the protocols can be realistically implemented over satellite links once either individual or passive collective attacks are assumed. Furthermore, splitting the satellite pass into discrete segments and extracting the key from each rather than from the overall single pass allows one to effectively improve robustness against the untrusted channel noise and establish a secure key under active collective attacks. We show that feasible amounts of optimized signal squeezing can substantially improve the applicability of the protocols allowing for lower system clock rates and aperture sizes and resulting in higher robustness against channel attenuation and noise compared to the coherent-state protocol.

Ultra Low-Noise FPGA-Based Six-Axis Optical Force–Torque Sensor: Hardware and Software

In this article, we present the novel hardware and software architecture of a smart optical force–torque sensor. The proposed configurable, modular, and compact electronics lead to performance characteristics that cannot be reached by currently available sensors: ultra-low noise with average noise power spectral density of 15 nV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sqrt{\text{Hz}}$</tex-math></inline-formula> over a signal bandwidth of 500 Hz, a resolution of 0.0001% full scale at a 95% confidence level, and a hardware latency of less than 100 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s. Performance is achieved by local synchronized oversampling of the sensor's optical transducers and parallel hardware processing of the sensor data using a field-programmable gate array (FPGA). The FPGA's reconfigurability provides for easy customization and updates; for example, by increasing the FPGA system clock rate to a maximum of 160 MHz, latency can be decreased to 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> s, limited by the current analog-to-digital converter. Furthermore, the approach is generic and could be duplicated with other types of transducers. An inertial measurement unit and a temperature sensor are integrated into the sensor electronics for gravity, inertia, and temperature compensations. Two software development kits that allow for the use of the sensor and its integration into the robot operating system have been developed and are discussed.

High-Fidelity Control of Superconducting Qubits Using Direct Microwave Synthesis in Higher Nyquist Zones

Control electronics for superconducting quantum processors have strict requirements for accurate command of the sensitive quantum states of their qubits. Hinging on the purity of ultra-phase-stable oscillators to upconvert very-low-noise baseband pulses, conventional control systems can become prohibitively complex and expensive when scaling to larger quantum devices, especially as high sampling rates become desirable for fine-grained pulse shaping. Few-GHz radio-frequency digital-to-analog converters (RF DACs) present a more economical avenue for high-fidelity control while simultaneously providing greater command over the spectrum of the synthesized signal. Modern RF DACs with extra-wide bandwidths are able to directly synthesize tones above their sampling rates, thereby keeping the system clock rate at a level compatible with modern digital logic systems while still being able to generate high-frequency pulses with arbitrary profiles. We have incorporated custom superconducting qubit control logic into off-the-shelf hardware capable of low-noise pulse synthesis up to 7.5 GHz using an RF DAC clocked at 5 GHz. Our approach enables highly linear and stable microwave synthesis over a wide bandwidth, giving rise to high-resolution control and a reduced number of required signal sources per qubit. We characterize the performance of the hardware using a five-transmon superconducting device and demonstrate consistently reduced two-qubit gate error (as low as 1.8%) which we show results from superior control chain linearity compared to traditional configurations. The exceptional flexibility and stability further establish a foundation for scalable quantum control beyond intermediate-scale devices.

A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry

A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.

A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA

The common solution for a field programmable gate array (FPGA)-based time-to-digital converter (TDC) is constructing a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of the delay elements of TDL determine the TDC time resolution. In this paper, we propose a dual-sampling TDL architecture and a bin decimation method that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve a high time resolution beyond the intrinsic cell delay. Two identical full hardware-based TDCs were implemented in a Xilinx UltraScale FPGA for performance evaluation. For fixed time intervals in the range from 0 to 440 ns, the average time-interval RMS resolution is measured by the two TDCs with 4.2 ps, thus the timestamp resolution of single TDC is derived as 2.97 ps. The maximum hit rate of the TDC is as high as half the system clock rate of FPGA, namely 250 MHz in our demo prototype. Because the conventional online bin-by-bin calibration is not needed, the implementation of the proposed TDC is straightforward and relatively resource-saving.

Bias-free true random number generation using superconducting nanowire single-photon detectors

We demonstrate a bias-free true random number generator (TRNG) based on single photon detection using superconducting nanowire single photon detectors (SNSPDs). By comparing the photon detection signals of two consecutive laser pulses and extracting the random bits by the von Neumann correction method, we achieved a random number generation efficiency of 25% (a generation rate of 3.75 Mbit s−1 at a system clock rate of 15 MHz). Using a multi-channel superconducting nanowire single photon detector system with controllable pulse signal amplitudes, we detected the single photons with photon number resolution and positional sensitivity, which could further increase the random number generation efficiency. In a three-channel SNSPD system, the random number bit generation efficiency was improved to 75%, corresponding to a generation rate of 7.5 Mbit s−1 with a 10 MHz system clock rate. All of the generated random numbers successfully passed the statistical test suite.

A Leakage Compensation Design for Low Supply Voltage SRAM

A leakage current compensation design for nanoscale SRAMs is proposed in this paper. The proposed compensation design is composed of a leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. At 0.6 V system voltage, the proposed compensation design reduces 27.86% of the average power dissipation, and 54.88% of the read delay at the expense of 3.64% area overhead. The proposed Static Random-Access Memory is implemented using the TSMC 40-nm CMOS logic technology. The energy per access is measured to be 0.9411 pJ given a 600-mV power supply and a 54-MHz system clock rate.

Реалізація криптографічних алгоритмів на основі ПЛІС для цифрових розподілених систем

This paper presents a single chip efficient FPGA implementation of RSA and DES for Digital Envelope Scheme that targets the Altera Apex 20KE EP20k200EBC356. Implementation of cryptographic algorithms on programmable devices like FPGAs run much faster than on software while preserving physical security of hardware solutions. The high throughput in the implementation of cryptographic algorithms for digital envelope scheme is achieved by means of exploiting the parallelism present in the DES and RSA operations as well as the features of Altera Apex 20KE device family which best suit for system-on-a-programmable-chip (SOPC) applications. The parallelized single chip implementation of DES and RSA for performing the Encryption/Decryption for the Digital envelope scheme offers a throughput of 3.5 Gbits/sec at a system clock rate of 54.7 MHz. This implementation even provides a means for using the DES and RSA separately.

Quantum key distribution over a 72 dB channel loss using ultralow dark count superconducting single-photon detectors.

We report the first quantum key distribution (QKD) experiment over a 72 dB channel loss using superconducting nanowire single-photon detectors (SSPD, SNSPD) with the dark count rate (DCR) of 0.01 cps. The DCR of the SSPD, which is dominated by the blackbody radiation at room temperature, is blocked by introducing cold optical bandpass filter. We employ the differential phase shift QKD (DPS-QKD) scheme with a 1 GHz system clock rate. The quantum bit error rate (QBER) below 3% is achieved when the length of the dispersion shifted fiber (DSF) is 336 km (72 dB loss), which is low enough to generate secure keys.

A Design Approach to Creating Scalable Video Processing Systems beyond UHDTV1 on an FPGA

An unquenchable end-user thirst for enhanced video quality results in ever-scaling video frame size and frame rate requirements. As we move from UHDTV1 to UHDTV2 and 120 frames/sec to 300 frames/sec, inevitably the computational complexity of video processing systems required to consume, process, and deliver video content increases. The need for solutions to support combinations of frame sizes and rates, as well as future increments, emphasizes the need for system scalability. The computational complexity and scalability requirements pose exciting challenges for field-programmable gate array (FPGA) implementation of video processing pipelines. This paper presents implementation techniques and methodologies to overcome these challenges. We specifically concentrate on architectures whereby the input per-pixel video sample rate exceeds the system clock rate. Novel results include classifying pixel processing orders and presenting a component-based design approach for future-proofing video processing solutions against an ever-scaling computational complexity requirement. Resource and memory bandwidth requirements of such systems are also analyzed and trends are presented.

2 GHz clock quantum key distribution over 260 km of standard telecom fiber

We report a demonstration of quantum key distribution (QKD) over a standard telecom fiber exceeding 50 dB in loss and 250 km in length. The differential phase shift QKD protocol was chosen and implemented with a 2 GHz system clock rate. By careful optimization of the 1 bit delayed Faraday-Michelson interferometer and the use of the superconducting single photon detector (SSPD), we achieved a quantum bit error rate below 2% when the fiber length was no more than 205 km, and of 3.45% for a 260 km fiber with 52.9 dB loss. We also improved the quantum efficiency of SSPD to obtain a high key rate for 50 km length.

IEEE 1149.1의 실시간 신호 시험 구조 설계

보드에 장착된 소자들을 테스트하기위해 제안된 IEEE 1149.1 시험 구조는 입력으로 TDI 핀을 사용하고 출력으로 TDO 핀을 사용하는 커다란 직렬 쉬프트 레지스터이다. IEEE 1149.1은 보드 수준에서의 테스트는 완벽하게 수행하지만 보드가 시스템에 장착되고 난 후의 수행 중인 시스템 수준에서의 실시간 동작클럭 속도로의 테스트에는 문제가 있다. 즉시험대상 핀의 실시간 동작신호를 시험하기 위하여 직렬 시프트 레지스트 체인들의 출력속도를 동작 클럭의 쉬프트레지스터 배수 이상의 속도로 작동 하여야 한다. 본 논문에서는 시스템 클럭과 동일한 속도로 실시간 신호를 캡쳐하기 위한 실시간 신호 시험 구조를 설계하고 시험 절차를 제안하였다. 제안한 실시간 신호 시험 구조를 Altera의 Max+Plus 10.0을 사용하여 제안한 시험 절차에 따라 시뮬레이션을 수행하였으며, 이를 통해 제안한 시험구조가 정확히 동작함을 확인하였다. IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

경계면스캔에서의 연속캡쳐 시험구조 개발

경계면스캔 구조는 시험대상회로의 입력측 스캔경로에 직렬입력을 통하여 시험패턴을 입력하고, 병렬로 대상회로에 인가한 후, 응답값을 출력측 스캔경로를 통하여 TDO로 직렬로 출력하는 시험구조로서, 대상회로의 동작속도에 맞추어 인가되는 연속적인 시험패턴에 대한 대상회로의 동적인 변화되는 출력을 관찰하는 것이 불가능하다. 본 논문에서는 대상회로의 동작속도 환경하에서 연속적인 시험패턴을 입력하여 시험대상회로의 연속적인 동적인 출력값들을 지속적으로 TDO로 출력함으로써 대상회로에 대한 성능시험에 사용할 수 있는 패턴생성기와 CBSR(Continuous capture Boundary Scan Register)를 이용한 시험구조와 시험절차를 개발하였다. 본 논문에서 사용된 CBSR은 연속캡쳐 설정과 쉬프트경로 설정을 위해 개발되었으며, 표준의 경계면 스캔 레지스터의 기능을 정상적으로 수행하도록 설계되었다. Altera의 Max+Plus 10.0를 사용하여 패턴생성기와 CBSR을 이용한 시험구조를 설계하고, 스캔구조를 적용 설계하고, CCAP명령어를 사용한 시험절차를 시뮬레이션을 통해 제안된 시험구조의 동작의 정확성을 확인하였다. In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

Steady-State and Dynamic Study of Active Power Filter With Efficient FPGA-Based Control Algorithm

A new approach using field-programmable gate array (FPGA) to implement a fully digital control algorithm of active power filter (APF) is proposed in this paper. This FPGA-based controller integrates the whole signal-processing function of an APF, including synchronous-reference-frame transform, low-pass filter, three-phase phase-locked loop, inverter-current controller, etc. By case studies on the principle, performance, and architecture, these control blocks are implemented in real-time and synthesized into a medium-scale FPGA chip by adopting some useful digital-signal-processing techniques, such as pipelining, folding and strength reduction, with respect to minimization of hardware resource and enhancement of operating frequency. As a result, the whole algorithm needs around 5000 logic elements and can run at synchronous system-clock rates of up to 65 MHz. Experimental results on a laboratory prototype are given to demonstrate performance of the proposed approach during steady-state and dynamic operations.

Effective correlation vector quantisation algorithm and its VLSI architecture

A correlation-inheriting vector quantisation (VQ) image coding algorithm is presented to re-encode the output indices of VQ after analysing the correlation inheritance of the indices&apos; neighbourhood. Simulation results indicate that this algorithm can compact the VQ index to achieve an ∼21:1 compression ratio on average. In accordance with this new algorithm, an efficient very large scale integration architecture is also derived that, after synthesis, achieves a system clock rate of 110 MHz using a 0.35 µm complementary metal-oxide-semiconductor standard library.

A concurrent spectral-screening PCT algorithm for remote sensing applications

Abstract The paper presents a concurrent algorithm for remote sensing applications that provides significant performance and image quality enhancements over conventional uniprocessor principal component transform (PCT) techniques. The algorithm combines spectral angle classification, principal component transform, and human centered color mapping. It is evaluated from an image quality perspective using images collected with the hyper-spectral digital imagery collection experiment (HYDICE) sensor, an airborne imaging spectrometer. These images correspond to foliated scenes taken from an altitude of 2000–7500 m at wavelengths between 400 nm and 2.5 μm. The scenes contain mechanized vehicles sitting in open fields as well as under camouflage. The algorithm operates with close to linear speedup on shared memory multiprocessors and can be readily extended to operate on multiple, low-cost PC-style servers connected with high-performance networking. A simple analytical model is outlined that allows the impact on performance of practical, application-specific properties to be assessed. These properties include image resolution, number of spectral bands, increases in the number of processors, changes in processor technology, networking speeds and system clock rates.

A reentrant delay-line memory using a YBa/sub 2/Cu/sub 3/O/sub 7-δ/ coplanar delay-line

The rapid growth in telecommunication traffic demands a higher-speed asynchronous transfer mode (ATM) switching system. At present, the upper limit of the system clock rate is determined by the maximum clock rate of conventional semiconductor memory devices, such as the register files used in ATM cell buffer storage. This is because the maximum clock rate of these register files is restricted by the propagation delay time between each register stage. Since a reentrant superconducting delay-line memory avoids this restriction using an analogue delay given by the superconducting delay line, we have proposed that this memory should be used in high-speed ATM cell buffer storage. Recently, we fabricated a 10-/spl mu/m-wide 37-cm-long YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// coplanar delay-line. This line had a delay of approximately 2.8 ns. Using this coplanar delay-line and an assembly of commercially available integrated circuits, we successfully developed superconducting delay-line memory. This memory operates as a 32-bit buffer storage at a clock rate of 10 GHz, which is several times faster than the register files. This result shows that the superconducting delay-line memory is a powerful candidate for high-speed ATM cell buffer storage.

Systolic design of frequency-domain block LMS adaptive digital filters

Adaptive filtering in the frequency domain can be achieved by Fourier transformation of the input signal and independent weighting of the contents of each frequency bin. In certain applications, filtering in the frequency domain results in great improvements in convergence rate over the conventional time-domain adaptive filtering. In this paper, the use of word-level systolic arrays to implement frequency-domain adaptive filters based on the complex least mean square (LMS) algorithm is described. The transform employed is the discrete Fourier transform (DFT). The proposed architecture operates on a block-by-block basis and makes use of the parallelism inherent in the computational problem under consideration. The input and output data flow sequentially and continuously into and out of the systolic arrays at the system clock rate. During each clock period, processing elements of three different types operate in parallel. The most computationally demanding among them performs only three consecutive multiplications and two addition/subtractions per clock period thereby allowing a very high throughput and very fast block signal processing to be achieved at the expense of a delay of 2 L+1 samples between the input and the output, L being the block size.

Impact of gate fan-in and fan-out limits on optoelectronic digital circuits

The impact of gate fan-in and fan-out limits on digital circuit delay is discussed with a set of benchmark circuits. This research presents the advantages of exploiting the ability of optoelectronic gates to perform both logic operations and optical interconnections with systematic optimization. It is possible for gate-level optical interconnected optoelectronic circuits to compete with their pure silicon counterparts in terms of the combinational circuit delay and system clock rate.