System Clock Rate Research Articles

Efficient digital filtering architectures using pipelining/interleaving

A pipelining/interleaving (PI) technique is developed for efficient digital filtering. By using a clock rate that is K times the data rate and with interleaved feedback of the output samples, a single expanded digital filter H(z/sup K/) can be made equivalent to a cascade of k identical filters H/sup k/(z) 1/spl les/k/spl les/K. The PI technique is used for designing Kalser-Hamming sharpened linear-phase FIR filters with very high performance. It can also be applied in efficient IIR filtering to alleviate the critical-loop limitation on system clock rates. Furthermore, the PI technique is applicable to designing efficient multirate signal processing systems.

Managing signal integrity [PCB design

As system clock rates race to 100 MHz and beyond, designers of printed-circuit boards and multichip modules must watch out for such high-speed effects as ground bounce, ringing, reflections, and crosstalk. The author describes how today's high-speed printed-circuit boards and multichip modules require integrated design systems that include signal integrity analysis tools.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optoelectronic time-of-flight design and the demonstration of an all-optical, stored program, digital computer

The recent demonstration of an all-optical, stored-program, digital computer by our group focused on high-speed optoelectronic design. It was made possible by a new digital design method known as time-of-flight design. A rudimentary, but general-purpose, proof of principle computer was built, which is all-optical in the sense that all signals connecting logic gates and all memory are optical in nature. LiNbO/sub 3/ directional couplers, electrooptic switches, are used to perform logic operations. In addition to demonstrating stored program operation in an optoelectronic digital computer, the system demonstrated the feasibility of the new design method, which does nor use any flip-flops or other bistable devices for synchronization or memory. This potentially allows system clock rates of the same order as device bandwidth. This paper describes how the time-of-flight design method was motivated by the special properties of optoelectronic digital design. The basic principles of the method we employed will be discussed along with some of its potential advantages. The experimental work with digital optical circuits leading up to and including the stored program computer experiment will then be discussed. Finally, the future potential of time-of-flight design in high-bandwidth optoelectronic systems will be discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The total delay fault model and statistical delay fault coverage

Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A quantitative delay fault coverage model to provide a figure of merit for delay testing is presented. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A new statistical delay fault coverage model is established. A defect level model is also proposed as a function of the yield of a manufacturing process and the new statistical delay fault coverage. A new delay testing strategy driven by the defect level for delay faults is proposed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-throughput nanolithography using an oxygen-plasma resistant two-layer resist system

LaB6-based electron beam nanolithography systems suffer from low beam current, resulting in low throughput for nanometer-sized patterns. This drawback is further aggravated by the low sensitivity of the standard high-resolution resist [poly(methylmethacrylate) (PMMA)] and by the reduction of intraproximity effect. We have investigated the lithography aspects (contrast, resolution, exposure latitude, throughput, and statistics) of two-layer resist systems consisting of a sensitive positive electron beam resist poly(3-butenyltrimethylsilane sulfone) (PBTMSS) as the top layer, and a variety of materials such as diamondlike carbon film or polyimide as the bottom layer. In these systems, exposed and developed PBTMSS is first oxidized to SiO2, which masks etching of the bottom layer. The pattern is in turn transferred to the substrate either by wet or dry etching using the bottom layer as a mask. Grating patterns with 0.2- and 0.1-μm pitch can be routinely fabricated on semiconductors, and 0.05-μm pitch patterns have been demonstrated. To achieve such high resolution, a low-strength developer is used, but a throughput about 30 to 50 times higher than that of PMMA can still be obtained. Gratings now can be patterned in a few hours over square-centimeter areas. Such a task would require days for PMMA. Implications of our results on lithography system clock rate and resist resolution–sensitivity tradeoff are also discussed.

Programmable DIMUS Processor

A 48-element, 256-beam, 25-kHz sample-rate programmable DIMUS processor is currently being constructed to work with a variety of arrays on the research platform FLIP. The design approach eliminates the need for a discretionary hard-wired steering matrix, while the system clock rate remains essentially the same as for a serial beamformer of conventional design. The processor is easily reprogrammed for different array configurations or for changes in the set of beam steering directions. Although the technique has been developed specifically for a single bit DIMUS beamformer (using clipped hydrophone outputs) it is equally applicable to multiple level Digital Multibeam Steering Systems.

Design of a Simulator for Investigating Organic Synchronization Systems

This paper describes circuits and devices designed for a real time simulator that was used to study a network synchronization scheme. The simulator represents a system of four geographically-separated stations with compound interconnections. The system clock rate is a function of the states of each local clock and the interconnecting paths. Component parts for the simulation system were built to specifications exceeding requirements of an actual system so that the operating states could be precisely determined. The simulator performed reliably during the series of experiments which provided the data described in a companion paper. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>