Phase Noise Of Synthesizer Research Articles

Application and Debugging of All-Digital Frequency Synthesizer

Presents the working principle of Integrated PLL chip Si4133, this paper presents the implementation of a 375MHz local oscillator for a super heterodyne transmitter/receiver by using Si4133.Using programming method to set the divider register Internal chip. In addition, this paper discuss the methods for decreases the phase noise. Debugging circuit using ICCAVR software , and show the debugging results. Facts show that the phase noise and spurious of the frequency synthesizer is low, and it is practical.

A 2.4 GHz low power CMOS transceiver for LR-WPAN applications

A 2.4 GHz low power transceiver for low-rate wireless personal area network (LR-WPAN) applications is presented. The optimized low-IF receiver consists of a novel current reuse RF front-end with an inductor-less-load balun LNA and quadrature mixer, and an adaptive analog baseband to reduce power and area. It achieves −94 dBm of sensitivity, −9 dBm of IIP3 and 28 dBc of image rejection. The phase-locked loop based direct phase modulated transmitter is proposed to reduce power and deliver a +3 dBm output power. The phase noise of the low power frequency synthesizer with current reuse stacked LC-VCO achieves −107.8 dBc/Hz at 1 MHz offset. An ultra-low power nonvolatile memory is used to store configuration data and save power. The chip is implemented in a 0.18 μm CMOS process, and the area is less than 2.8 mm2. The transceiver consumes only 10.98 mW in the receiving mode and 13.32 mW in the transmitting mode.

A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology

A fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) is proposed. Through a particular symmetrical coupling network formed by diode-connected transistors, the in-phase coupling is realized in the IPIC-QVCO, which reduces both phase noise and phase error. A compact inductor-less divider chain is designed to reduce power consumption. A self-correcting low spur charge pump is employed to reduce reference spur. A standalone 60 GHz IPIC-QVCO and a fully integrated PLL are implemented in standard 65 nm low power CMOS technology. The measurement results show that the QVCO covers a frequency range from 57.88 to 68.33 GHz while consuming 11.4 mW power from a 1.2 V supply. The phase noise of the QVCO is -92 ~ -95 dBc/Hz at 1 MHz offset. The FOM and FOM T of the QVCO are -178.1 ~ -179.7 and -182.5 ~ -184.1 dBc/Hz respectively. The tuning range of the frequency synthesizer is from 57.9 to 68.3 GHz, and the power consumption is 24.6 mW. The phase noise of the frequency synthesizer is -89.8 ~ -91.5 dBc/Hz at 1 MHz offset across the frequency band.

An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application

A wide-band fully differential fractional-N frequency synthesizer for multi-standard application is presented. The single fully differential LC---VCO with 28.5 % tuning rang and a set of dividers, quadrature self-mixer are designed to accomplish the multi-frequency bands with the frequency band from 0.38 to 6 GHz and from 9.0 to 12 GHz. It covers several wireless standards. A novel high isolation multiplexer is presented to achieve the frequency band selection. This chip was implemented with 65 nm CMOS technology and the maximum consumption is 20.05 mA from 1.2 V power supply. It occupies an active area of 1.5 mm2. The measured typical phase noise of the frequency synthesizer is ?114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output.

OFDM Inter-carrier Interference Due to Radio Frequency Synthesizer Phase Noise

Abstract This work presents the effects of radio-frequency Local Oscillator non-idealities on OFDM inter-carrier interference. The synthesizer has the main role on modulation and demodulation process of base band IQ signals to radio frequency channels which need to fulfill several requirements imposed by standards specifications. Phase and frequency stability are crucial, since the synchronization of the entire system depends on the accuracy of this circuit. The discussed OFDM system is based on a simulation scenario including radio-frequency channel conversion considering Local Oscillator with configurable phase noise power and bandwidth. This feature allows the study of global system based on Local Oscillator output spectrum. Sub-channel spacing, cyclic redundancy and pulse shaping are configurable. The obtained results indicate that free run oscillator phase noise characterization is not appropriate when the Local Oscillator in the radio-frequency front end is based on synthesizer architecture. System evaluation is based on error vector magnitude. The relation of this metric with the Local Oscillator phase noise allows the performance estimation of the global system.

A UHF-RFID Transceiver With a Blocker-Canceller Feedback and $+$30 dBm Output Power

A single chip UHF-RFID transceiver front-end is presented. The chip was designed according to EPCglobal Class-1 Gen-2 and supports both ETSI and FCC requirements. The receiver front end is capable of rejecting self-jammers as large as <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> 10 dBm with the aid of a feedback loop. The stability and the robustness of the loop and other system requirements are studied. A <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$+$</tex></formula> 30 dBm class-AB power amplifier (PA) with 28% PAE is also integrated on the chip. The pseudo differential architecture of the PA greatly reduces the injection of the signal into the substrate. A simple model is used to estimate the effect of the substrate noise injection by the PA on the receiving circuit modules and design guides are given. The chip is fabricated in a standard 0.18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> CMOS process and occupies an area of 6 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${\rm mm}^{2}$</tex></formula> . The receiver sensitivity in the talk mode with the transmission of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex></formula> 30 dBm output power by the PA is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 87.4 dBm at the presence of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$+$</tex> </formula> 10 dBm self-jammer. The synthesizer phase noise at 800 kHz offset is better than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 128 dBc/Hz and the PA satisfies the required spectrum mask when outputting an AM modulated signal at the maximum output power. The chip, excluding the PA, draws 51 mA from a 1.8 V supply.

Parametric Analysis to Reduce Phase Noise of Frequency Synthesizers for Wireless Communication System

The aim of this paper is analysis and presenting a technique to reduce phase noise of frequency synthesizer for pure signal synthesis. To reduce phase noise of synthesizer, first, we present a mathematical and accurate model of phase noise in phase locked loop based frequency synthesizer with take into account noise of its component. Then we predict output phase noise in term of its parameters. Finally, we describe as effective technique for phase noise in frequency synthesizer. The simulation results show the performance of the frequency synthesizer for the High Speed communication system.

A Phase Noise Analysis Method for Millimeter-Wave Passive Imager BHU-2D-U Frequency Synthesizer

A nontrivial phase noise analysis method is proposed for frequency synthesizer of a passive millimeter-wave synthetic aperture interferometric radiometer (SAIR) imager for concealed weapon detections on human bodies with high imaging rates. The frequency synthesizer provides local oscillator signals for both millimeter-wave front ends and intermediate frequency IQ demodulators for the SAIR system. The influence of synthesizer phase noise in different offset frequency ranges on the visibility phase errors has been systematically investigated with noise requirements drawn, and the integrated RMS phase error could represent uncorrelated phase noise effects in the most critical offset frequency range for visibility error control. An analytical phase noise simulation method is proposed to guide synthesizer design. To conclude, the phase noise effects on SAIR visibility errors have been concretized to noise design requirements, and good agreements have been observed between simulation and measurement results. The frequency synthesizer designed has been successfully in operation in BHU-2D-U system.

Consideration on offset LO contribution in the phase noise of offset PLL architecture

ABSTRACTBased on experimental results, the phase noise of offset phase locked loop (PLL) is analyzed theoretically and experimented. Analyses are developed both to calculate the in‐band phase noise of a given synthesizer architecture and to predict the impact from the the phase noise of offset local oscillator (LO). This article verifies that the phase noise of offset LO give a direct impact on the in‐band phase noise of frequency synthesizer. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2699–2701, 2013

A Wideband Frequency Synthesizer with High Frequency Resolution

ABSTRACTThis article presents the design and implementation of a wideband frequency synthesizer which uses a direct digital synthesis as a fractional divider in the phase‐locked loop. The frequency resolution is 7.1 × 10−5 Hz. A phase‐domain model of this synthesizer is analyzed and simulated. A formula of output phase noise is derived. The output phase noise of synthesizer is −124 dBc/Hz (10 kHz offset) at the frequency of 1 GHz. The frequency synthesizer model has been designed with advantages of wide bandwidth, low phase noise, high‐frequency resolution, low spurious, high frequency stability, and simple structure. With frequency multiplier and divider module, the frequency band of synthesizer can be extended from 250 MHz to 8 GHz. The module is suitable for communication instrument. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2454–2457, 2013

고해상도 영상레이더 성능 분석을 위한 모델링 및 시뮬레이션 기법

In this paper, modeling and simulation for performance analysis of high resolution SAR system has been carried out in the time, frequency and numeric domain using ADS Ptolemy simulation tool of Agilent corporation. SAR system consists of antenna, controller and transceiver. Error parameters affecting SAR system performances have been defined, modeled and simulated such as phase noise of frequency synthesizer, amplitude and phase characteristic of TWTA, sampling frequency of waveform generator and I/Q imbalance. Finally, the development requirements of SAR system based on the impulse response function have been derived.

Analysis of Phase Noise in Phase/Frequency Detectors

The phase noise of phase/frequency detectors can significantly raise the in-band phase noise of frequency synthesizers, corrupting the modulated signal. This paper analyzes the phase noise mechanisms in CMOS phase/frequency detectors and applies the results to two different topologies. It is shown that an octave increase in the input frequency raises the phase noise by 6 dB if flicker noise is dominant and by 3 dB if white noise is dominant. An optimization methodology is also proposed that lowers the phase noise by 4 to 8 dB for a given power consumption. Simulation and analytical results agree to within 3.1 dB for the two topologies at different frequencies.

Fractional Frequency Synthesizers With Low Order Time-Variant Digital Sigma-Delta Modulator

This paper proposes the use of a digital ΣΔ modulator with pseudorandom variation of coefficients. The method improves PLL-based Fractional Frequency Synthesizer's performance while using a low order digital ΣΔ modulator. The time variant coefficients, in a low order digital ΣΔ modulator, significantly enlarge the pseudorandom output pattern period thus avoiding critical spur tones in the fractional synthesizer's phase-noise. Behavioral simulations let us verify that the proposed technique operates better than a higher order modulator with additive dither. With a low order ΣΔ architecture, the programmable divider phase-selection logic and frequency range of operation parameters can be relaxed.

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 μs over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of −193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about −115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than −52 dBc. The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.

Impact of Transceiver RFIC Impairments on MIMO System Performance

This paper addresses the performance degradation of multiple-input multiple-output (MIMO) communication systems due to MIMO wireless transceiver radio frequency integrated circuits (RFIC) imperfections. The effects of signal coupling in RF front-end, frequency synthesizer phase noise, and the gain imbalance between different radio paths are investigated. These issues are explored by analytical derivations and results are verified by Monte Carlo simulations. The analytical model achieves a good agreement with the simulation results. The conclusion can serve as a useful reference for MIMO RFIC designers.

A ${\hbox{70}}{\hbox{–}} {\hbox{78-}}{\hbox{GHz}}$ Integrated CMOS Frequency Synthesizer for $W$-Band Satellite Communications

A 70-78-GHz integrated frequency synthesizer is implemented in 65-nm CMOS. It has been integrated in a two-step zero-IF millimeter-wave transceiver for emerging applications, such as 81-86-GHz satellite communication, short-distance high-speed wireless link, as well as imaging and radar. The transceiver utilizes synthesizer voltage-controlled oscillator (VCO) output as the first LO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</sub> and 1/8 of LO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</sub> as the second LO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</sub> to cover the desired frequency band. The proposed synthesizer adopts integer-N architecture with 50-MHz reference. It also features coarse phase rotation to provide beam-forming capability for the intended transceiver. The synthesizer phase noise (PN) has been measured at 1/8 of the VCO frequency, about -102.2 dBc/Hz @ 1-MHz offset, and the measured reference spur for LO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</sub> is less than -49 dBc. Thus, the extrapolated PN performance is better than -84 dBc/Hz @ 1 MHz at 70-78 GHz LO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RF</sub> . The embedded frequency synthesizer occupies 0.16-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area, including the angular rotator and buffers, and consumes 65 mW under 1-V supply.

A 8.75–11.2-GHz, low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented. The mathematical models for the behavior of the synthesizer's spur and phase noise are analyzed, and the optimization methodology is proposed. Measurement results exhibits that the frequency synthesizer's integrated phase noise is less than 1° (1 kHz to 100 MHz) with a 4.375 GHz carrier (after divide-by-2), and the reference frequency spur is below −60 dBc operating with a 33 MHz reference clock. The frequency synthesizer is fabricated on a standard 0.13 μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.

Analysis of Optimum Detector of Trellis Coded MPSK in Phase Noise Channels

This paper presents a novel analytical expression which approximates the bit error rate (BER) of the joint phase and symbol maximum a posteriori (JMAP) sequence estimator for: trellis code modulation (TCM) with M-ary phase shift keying (MPSK) modulation; any arbitrary phase noise model (i.e., not limited to the Wiener process); and either a matched or mismatched decoder. First, we derived convenient closed-form expressions for approximating the pairwise error probability of two code sequences for both matched and mismatched decoders. Since the expressions are formulated either in the time or in the frequency domain, it is possible to indicate the contribution of every frequency in the phase noise spectrum. We then applied the union bound on the code sequence pairwise errors. The analytical expression was tight (usually <;1dB) for MPSK constellations with M ≥ 4 and code rates ≥ 0.5. Once developed, the expressions will assist designers to consider the influence on receiver performance of the code characteristics, decoder implementation and RF synthesizer phase noise. It further enables joint optimization of the RF synthesizer, the code and the decoder for achieving the lowest error rate or other design targets.

Optimized reduction of spur tones in fractional frequency synthesizers

In this article the contribution of the digital $$\Upsigma\Updelta$$ modulator in fractional frequency synthesizers is explored. Due to the circuit's non linear behavior, the spur tones generated by the digital $$\Upsigma\Updelta$$ modulation degrade the synthesizer's phase noise even in regions where the charge pump noise is dominant. A new method to dither digital MASH $$\Upsigma\Updelta$$ modulators for fractional frequency synthesizers is proposed. The method barely increases the circuit complexity and has the same performance as more cumbersome architectures. Also, a new design consideration to linearize the voltage control oscillator is proposed. Experimental results are obtained in an on-chip fractional synthesizer manufactured in CMOS technology.

A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications

Supply voltage reduction with process scaling has made the design of analog, RF and mixed mode circuits increasingly difficult. In this paper, we present the design of an ultra-low voltage, low power and highly integrated dual-mode receiver for 2.4-GHz ISM-band applications. The receiver operates reliably from 0.55-0.65 V and is compatible with commercial standards such as Bluetooth and ZigBee. We discuss the design challenges at low voltage supplies such as limited fT for transistors and higher nonlinearities due to limited available signal swing, and present the architectural and circuit level design techniques used to overcome these challenges. The highly integrated receiver prototype chip contains RF front-end circuits, analog baseband circuits and the RF frequency synthesizer and was fabricated in a standard digital 90-nm CMOS process; it achieves a gain of 67 dB, noise figure of 16 dB, IIP3 of -10.5 dBm, synthesizer phase noise of - 127 dBc/Hz at 3-MHz offset, consumes 32.5 mW from 0.6 V and occupies an active area of 1.7 mm2.