Synthesis Of Circuits Research Articles

Development of a digital signal processing model using a frequency synthesizer and synthesis of quadrature conversion circuits

An important issue of improving the quality of the functioning of measuring systems is the improvement of the conversion methods and the algorithmization of the processes for eliminating various noises and interferences that arise in the tasks of analog-to-digital information conversion.The article analyzes the algorithms for assessing the accuracy of digital signal processing (DSP) in a complex of issues due to the development of digital and digital-analog element base, as well as the development of methods and algorithms for processing and generating signals.

Asynchronous Circuit Principles and a Survey of Associated Design Tools

Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perhaps even sub-nano geometries, the design process complicates accordingly. Once subtle in higher geometry nodes, some effects become relevant or even dominant. Examples are effects that tamper the reliability of wires, such as crosstalk, or the adequate behaviour of gates, such as the increasing sensitivity to single event effects. Design techniques must thus also evolve, to provide a wide range of tools to deal with new effects during the integrated circuit design and test processes. This tutorial covers one set of design techniques that is often overlooked, but which can reveal themselves instrumental in dealing with the mentioned technology evolution, the use of clockless or asynchronous circuits. The tutorial is divided into three parts: first it introduces a metamodel for the digital circuit design process enabling to reason about distinct design styles; second, it covers the main principles of asynchronous circuit design, differentiating it from mainstream circuit design techniques such as conventional synchronous design; the third and last part presents a set of tools and systems that can be employed to effectively design asynchronous design, with emphasis on material that can be used to produce manufacturable circuits and systems, often associated to commercial integrated circuit synthesis, implementation and test tools and frameworks.

Optimal SAT Solver Synthesis of Quantum Circuits Representing Cryptographic Nonlinear Functions

Optimal SAT Solver Synthesis of Quantum Circuits Representing Cryptographic Nonlinear Functions

Synthesis of reversible circuits consisting of NOT, CNOT and 2-CNOT gates with small number of additional inputs

Article Synthesis of reversible circuits consisting of NOT, CNOT and 2-CNOT gates with small number of additional inputs was published on December 1, 2022 in the journal Discrete Mathematics and Applications (volume 32, issue 6).

Cost-efficient method for inverter reduction and proper placement in quantum-dot cellular automata

ABSTRACT The Quantum-dot Cellular Automata (QCA), an emerging technology, is observed to be the most viable solution to current CMOS. It is capable of finding solutions to challenges, like high power consumptionand device density. The elementary logic primitives are the majority gate, inverter and wire. In QCA, two different event cell orientations for the realisation of the inverter are available, where the diagonally oriented structure (DOS) is mostly utilised in logic synthesis. However, considering the cell misalignment and displacement, the DOS prevails with a more stable polarised output. But the use of DOS increases cell count which increases the area of the circuit. So, it is desirable to minimise the inverter in a circuit due to the non-availability of the simple logic unit of the inverter. In this paper, two algorithms are proposed for the synthesis of cost-efficient QCA circuits from any boolean function to minimize logic primitives. The proposed role-based mechanism for boolean function synthesis results in the reduction of inverter gate, circuit size, QCA cost and power dissipation. The efficiency of the proposed algorithms has been verified with the realization of standard functions, adders and symmetric functions. A significant improvement in inverter reduction has been reported.

Physical constraint-aware CNOT quantum circuit synthesis and optimization

Physical constraint-aware CNOT quantum circuit synthesis and optimization

On a Hypothetical Model with Second Kind Chebyshev’s Polynomial–Correction: Type of Limit Cycles, Simulations, and Possible Applications

In this article, we explore a new extended Lienard-type planar system with “corrections” of the second kind Chebyshev’s polynomial Un. The number and type of limit cycles are also studied. The discussion on the y(t)—component of the solution of the Lienard system is connected to searching for the solution of the synthesis of filters and electrical circuits. Numerical experiments, depicting our outcomes using CAS MATHEMATICA, are presented.

Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning

This article presents a novel deep-reinforcement-learning-based method for topology synthesis of analog-integrated circuits, especially operational amplifiers (OpAmps). It behaves like a human designer, who learns from trials, derives design knowledge and experience, and evolves gradually to finally figure out optimal manners to construct proper circuit topologies that meet design specifications. Essential design rules are defined and applied to set up the specialized environment for reinforcement learning in order to reasonably construct circuit topologies with building blocks as the basic components. Our proposed method can not only handle large-size circuit designs but also generate creative circuit topologies. The produced circuit topologies are verified by the simulation-in-loop sizing. In order to improve the evaluation efficiency, hash table and symbolic analysis techniques are utilized to significantly reduce the number of the produced topologies to be sized during the synthesis process. Compared with the state-of-the-art approaches, our proposed method significantly improves the synthesis efficiency by consuming only several hours on average to produce a trustworthy solution. Our experimental results demonstrate its sound efficiency, strong reliability, and wide applicability.

Solving the Schrödinger Equation with Genetic Algorithms: A Practical Approach

The Schrödinger equation is one of the most important equations in physics and chemistry and can be solved in the simplest cases by computer numerical methods. Since the beginning of the 1970s, the computer began to be used to solve this equation in elementary quantum systems, and, in the most complex case, a ‘hydrogen-like’ system. Obtaining the solution means finding the wave function, which allows predicting the physical and chemical properties of the quantum system. However, when a quantum system is more complex than a ‘hydrogen-like’ system, we must be satisfied with an approximate solution of the equation. During the last decade, application of algorithms and principles of quantum computation in disciplines other than physics and chemistry, such as biology and artificial intelligence, has led to the search for alternative techniques with which to obtain approximate solutions of the Schrödinger equation. In this work, we review and illustrate the application of genetic algorithms, i.e., stochastic optimization procedures inspired by Darwinian evolution, in elementary quantum systems and in quantum models of artificial intelligence. In this last field, we illustrate with two ‘toy models’ how to solve the Schrödinger equation in an elementary model of a quantum neuron and in the synthesis of quantum circuits controlling the behavior of a Braitenberg vehicle.

Bayesian Optimization Approach for RF Circuit Synthesis via Multitask Neural Network Enhanced Gaussian Process

An RF integrated circuit design heavily relies upon experienced experts to iteratively tune the circuit parameters. A Bayesian optimization (BO) method is explored in existing works for automated analog and RF circuit synthesis. The overall performance can be further improved by constructing a model to exploit the correlation among different circuit specifications. In this article, we propose a BO approach for RF circuit synthesis via a multitask neural network enhanced Gaussian process (MTNN-GP). We present a novel multioutput GP model, in which the kernel functions of multiple outputs are constructed from a multitask neural network with shared hidden layers and task-specific layers. Therefore, the correlation between the outputs can be captured by the shared hidden layers. Our proposed MTNN-GP-based BO method is compared with several state-of-the-art BO methods on three real word RF circuits and achieves best performance. The experimental results demonstrate the effectiveness and efficiency of our proposed method.

Improving tools for diagnosing technical condition of ship electric power installations

Existing information-measuring systems (IMS) do not fully correspond to the tasks of monitoring electric power installations (EPI) in terms of their characteristics. The capabilities of IMS have certain limitations regarding the probability of measurement results and the degree of invariance to the influence of operational factors. This proves that for modern failure-free EPI technical operation, new diagnostic tools are in demand. Such means should be seamlessly integrated in IMS to enable high operational efficiency and performance reliability. Therefore, it is of particular relevance to tackle the scientific and technical issue of rational combination of protection and preservation of the characteristics of fiber-optic sensors of relative humidity control systems in ship EPI. To solve the problem, the chosen object of this study is the processes of formation and transformation of the diagnostic signal in the means of humidity control. It has been established that the improvement of the characteristics of the control means can be achieved through the synthesis of known optical circuits and the latest materials. To register the parameters of relative humidity, a new circuitry solution was proposed for the sensor based on fiber-optic and elements made of nanomaterials. The main feature of the proposed monitoring tool is invariance to operational destabilizing factors. The scope of application of the obtained research results involves distributed fiber-optic systems for monitoring the technical condition of ship electric power systems. The introduction of a new means for measuring humidity will make it possible to achieve an increase in the efficiency of use and reliability of EPI by reducing the accident rate by 6...11 %, as well as a decrease in operating costs by USD 8...10 per 1 kWh of generated power per year of operation with an average load

Increasing-Dimension Evolution: Make the evolutionary design of passive filters more efficient

Evolutionary circuit design is a promising way to achieve the automatic synthesis of analog circuits, and passive filters are essential circuits that must be considered. For now, in the evolutionary design of passive filters, the size control of filters under practical difficulty is still an important issue to be studied. This paper proposed a search strategy called Increasing-Dimension Evolution (IDE). The strategy introduces the concepts of exon and intron to control gene expression levels in evolutionary search. Through this strategy, even if the length of the chromosome is fixed, the search engine can effectively search up multiple design spaces and find a small circuit size at low computing costs. We built an effective evolutionary filter design model using the IDE strategy. Experimental results show that the proposed strategy can obtain filter sizes comparable to advanced conventional design methods for several passive filter design tasks with practical difficulties. In addition, the strategy makes the search engine more effective in a given complex task, and this task is difficult to be directly solved using conventional design methods.

ARASP: An ASIP Processor for Automated Reversible Logic Synthesis

Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.

SYNTHESIS OF THE FINITE STATE MACHINE WITH DATAPATH OF TRANSITIONS ACCORDING TO THE OPERATIONAL TABLE OF TRANSITIONS

Context. The problem of formalizing the description of a microprogram finite state machine based on the principle of operational transformation of state codes with the help of a modified transition table is considered. The object of research was a model of a microprogram finite state machine with datapath of transitions.
 Objective. The goal of the work is development and research of a method for formally specifying a microprogram finite state machine with datapath of transitions in the form of a modified table of transitions containing sufficient information for synthesizing the logic circuit of the finite state machine in the basis of programmable logic devices.
 Method. A new way of representing the formal solution of the problem of algebraic synthesis of a microprogram finite state machine with datapath of transitions in the form of an operational table of transitions is proposed. This table is a modification of the direct structural table traditionally used in the synthesis of microprogram finite state machines. The use of the previously known representation of the formal solution of the problem of algebraic synthesis in the form of a system of isomorphisms of automaton algebras is too formalized and makes it difficult to synthesize the logical circuit of the finite state machine due to the separate description of the transition and output functions. It is shown that the structure of a microprogram finite state machine with datapath of transitions requires information about the set of interpretations of state codes and the transition operations used to be entered into the traditional table of transitions. It is noted that the proposed operational table of transitions contains sufficient information for the synthesis of the logical circuit of the finite state machine. An example of constructing an operational table of transitions for a finite state machine given by a graph-scheme of the implemented control algorithm is shown. The example demonstrates various ways to interpret state codes. The procedure for synthesizing the circuit for generating codes of transition operations and the circuit for generating microoperations according to the operational table of transitions is proposed.
 Results. An example of the implementation of the main stages of the synthesis of a finite state machine with datapath of transitions according to the operational table of transitions is considered. Examples of synthesized finite state machine models in the VHDL language are given, which take into account the peculiarities of the representation of finite state machine models in Xilinx Vivado CAD. The results of the synthesis of the finite state machine according to VHDL models in FPGA basis are shown.
 Conclusions. The experiments carried out confirmed the sufficiency of the operational table of transitions for describing a microprogram finite state machine with operational transformation of state codes for the purpose of further synthesizing its logic circuit. Prospects for further research are the use of the proposed operational table of transitions in the development of various methods for the synthesis and optimization of microprogram finite state machine with operational transformation of state codes.

Quantum reversible circuits for mathrm{GF}(2^{8}) multiplicative inverse

The synthesis of quantum circuits for multiplicative inverse over operatorname{GF}(2^{8}) are discussed in this paper. We first convert the multiplicative inverse operation in operatorname{GF}(2^{8}) to arithmetic operations in the composite field operatorname{GF}((2^{4})^{2}), and then discuss the expressions of the square calculation, the inversion calculation and the multiplication calculation separately in the finite field operatorname{GF}(2^{4}), where the expressions of multiplication calculation in operatorname{GF}(2^{4}) are given directly in operatorname{GF}(2^{4}) and given through being transformed into the composite field operatorname{GF}((2^{2})^{2}). Then the quantum circuits of these calculations are realized one by one. Finally, two quantum circuits for multiplicative inverse over operatorname{GF}(2^{8}) are synthesized. They both use 21 qubits, the first quantum circuit uses 55 Toffoli gates and 107 CNOT gates and the second one uses 37 Toffoli gates and 209 CNOT gates. As an example of the application of multiplication inverse, we apply these quantum circuits to the implementations of the S-box quantum circuit of the AES cryptographic algorithm. Two quantum circuits for implementing the S-box of the AES cryptographic algorithm are presented. The first quantum circuit uses 21 qubits, 55 Toffoli gates, 131 CNOT gates and 4 NOT gates and the second one uses 21 qubits, 37 Toffoli gates, 233 CNOT gates and 4 NOT gates. Through the evaluation of quantum cost, the two quantum circuits of the S-box of AES cryptographic algorithm use less quantum resources than the existing schemes.

ILP-Based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis

Approximate computing is a promising approach to the design of area–power-performance-efficient circuits for computation error-tolerant applications such as image processing and machine learning. Approximate functional units, such as approximate adders and approximate multipliers, have been actively studied for the past decade, and some of these approximate functional units can dynamically change the degree of computation accuracy. The greater their computational inaccuracy, the faster they are. This study examined the high-level synthesis of approximate circuits that take advantage of such accuracy-controllable functional units. Scheduling methods based on integer linear programming (ILP) and list scheduling were proposed. Under resource and time constraints, the proposed method tries to minimize the computation error of the output value by selectively multi-cycling operations. Operations that have a large impact on the output accuracy are multi-cycled to perform exact computing, whereas operations with a small impact on the accuracy are assigned a single cycle for approximate computing. In the experiments, we explored the trade-off between performance, hardware cost, and accuracy to demonstrate the effectiveness of this work.

Creating and balancing the paths of arbiter-based physically unclonable functions on FPGA

Objectives. The problem of constructing a new structure of paths of physically unclonable function of the arbiter type (APUF) on the FPGA is being solved, based on the full use of internal resources of LUT-blocks, which are functionally repeaters. The relevance of the study is associated with the rapid development of physical cryptography tools. Another goal is the developing a methodology for eliminating the asymmetry of the APUF paths associated with the peculiarity of the synthesis of such circuits on the FPGA.Methods. The methods of synthesis of digital devices, their parametric modeling and implementation on rapid prototyping boards are used. A ring oscillator circuit is used to measure the internal propagation delays of signals through the APUF paths.Results. A new structure of the basic element of APUF paths with the use of two functional repeaters is proposed. The necessity of balancing the delays of APUF paths is demonstrated. A technique has been developed to eliminate the asymmetry of signal propagation through APUF paths based on controlled delay lines. The disadvantages of classical approaches as an APUF arbitrator and the need for their modification are shown.Conclusion. The proposed approach to build APUF paths has shown its viability and promise. An improvement in the characteristics of APUF constructed according to the proposed method, as well as a reduction in hardware costs during their implementation compared to classical APUF schemes, is experimentally confirmed. It seems promising to develop the described methodology for constructing the APUF to improve the structure of the arbiter.

Cost-effective synthesis of QCA logic circuit using genetic algorithm

Cost-effective synthesis of QCA logic circuit using genetic algorithm

Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words

The problem of synthesis of combinational circuits of code converters designed to reduce the length of words from a given set of encoded binary words is considered. The encoding assumes that different binary words will be encoded by different binary codes of shorter length. Code converters of this type are designed to reduce the length of binary words transmitted in digital systems over data buses when the bit depth of the transmitted words exceeds the bit depth of the data bus. For example, 18-bit or 17-bit words need to be transmitted over a 16-bit data bus. Each such word can be transmitted in two cycles of operation of a digital system, however, this approach reduces the overall performance of the system. One of the approaches to solve such problems is the development of combinational circuits that convert long binary encoded words into shorter ones. The proposed methods for solving the problem of synthesizing circuits of code converters are based on the compilation and logical minimization of such forms of systems of incompletely specified Boolean functions as disjunc­tive normal forms (DNF) and binary decision diagrams (BDD). Using BDD to minimize representations of k-valued functions that depend on Boolean variables is also proposed. Technologically independent logical minimization of functional descriptions of the designed code converters is proposed to be performed by programs for minimizing systems of Boolean functions in the DNF class and programs for joint minimization of BDD representations of systems of completely specified Boolean functions. Minimization of functional descriptions is aimed at reducing the hardware complexity of combinational circuits in the basis of library elements or programmable FPGA elements implementing code converters of the class in question.

Fast Design Space Exploration of Nonlinear Systems: Part II

Nonlinear system design is often a multiobjective optimization problem involving the search for a design that satisfies a number of predefined constraints. The design space is typically very large since it includes all possible system architectures with different combinations of components composing each architecture. In this article, we address nonlinear system design space exploration through a two-step approach encapsulated in a framework called fast design space exploration of nonlinear systems (ASSENT). In the first step, we use a genetic algorithm to search for system architectures that allow discrete choices for component values or else only component values for a fixed architecture. This step yields a coarse design since the system may or may not meet the target specifications. In contrast to prior works on design space exploration that rely on forward design, we use an inverse design in step 2 to search over a continuous space and fine-tune the component values with the goal of improving the value of the objective function. We use a neural network (NN) to model the system response. The NN is converted into a mixed-integer linear program for active learning to sample component values efficiently. We illustrate the efficacy of ASSENT on problems ranging from nonlinear system design to the design of electrical circuits. Experimental results show that ASSENT achieves the same or better value of the objective function compared to various other optimization techniques for nonlinear system design by up to 53%. We improve sample efficiency by 6– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12\times $ </tex-math></inline-formula> compared to reinforcement learning-based synthesis of electrical circuits.