Synchronous Reference Frame Phase-locked Loop Research Articles

Compensation characterization of the UPQC system under an improved nonlinear controller based on the MSTOGI-PLL device

To solve the delay problem of a unified power quality conditioner (UPQC) system during the separation of the fundamental positive-order components and to better filter out the DC and harmonic components to realize accurate phase locking, a mixed second- and third-order generalized integrator phase-locked loop (MSTOGI-PLL) has been designed to replace the traditional synchronous reference frame phase-locked loop (SRF-PLL). Under the premise of adopting the new phase-locking device of MSTOGI-PLL, the active disturbance rejection control (ADRC) controller or the super-twisting algorithm (STA) sliding mode controller is used in the DC voltage control module instead of the traditional PI controller, and the suitability of the two nonlinear controllers with the MSTOGI-PLL device is investigated. First, the new MSTOGI-PLL device is designed, and the new phase-locking method is applied to make the UPQC realize accurate phase locking under the non-ideal situation of the grid voltage containing unbalance, DC component, harmonics, and so on. Based on the above foundation, the ADRC or STA controller is independently adopted to replace the PI controller to construct the UPQC system with the ADRC + MSTOGI phase-locking device and the second-order STA + MSTOGI phase-locking device. Finally, a simulation comparison is carried out in a Simulink simulation platform regarding the UPQC system under different phase-locking devices, and the simulation results demonstrate that MSTOGI-PLL can successfully filter out the DC component and resolve the phase-locking process delay issue. Additionally, the UPQC system with ADRC + MSTOGI-PLL exhibits superior immunity and response speed to the PI controller and the second-order STA controller.

Nonlinear analysis of the synchronous reference frame phase-locked loop under unbalanced grid voltage

The synchronous reference frame phase-locked loop (SRF-PLL), also called dqPLL, is an electric circuit commonly used in power electronics to estimate the phase angle of a three-phase AC grid. If the voltage is unbalanced, the PLL is modeled as a periodically forced nonlinear oscillator and is known in practice to converge to a steady oscillation. In the existing literature, the oscillation has been studied via linearization assuming a low level of unbalance. Aiming for stronger nonlocal statements, we present nonlinear analysis. We apply the method of autonomous comparison systems and incremental stability to show that the steady oscillation is unique and attractive in a wider neighborhood. Its lock-in domain is estimated using numerical phase portrait analysis. The oscillation is further approximated up to the terms of the second order in the unbalance factor—it yields an estimation of the time average of the PLL’s phase error which is not visible by linearization only. The results provide stability guarantees and can guide the tuning of SRF-PLL.

Accurate Stability Analysis of Three-Phase Converter System Connected to Weak Grid under Coordinate System Transformation

This paper studies the simplified impedance criterion of the three-phase converter system in different coordinate systems. In addition, the influence of small signal stability of converter units under the weak grid is discussed in three-phase converter systems. Firstly, a small signal model of a three-phase grid-connected converter system is established based on the voltage and current double closed-loop control strategy in dq real coordinate system and the dynamic characteristics of SRF-PLL (Synchronous Reference Frame Phase-Locked Loop). Then, based on the coordinate transformation, the admittance models in the dq real coordinate system and the fb complex coordinate system are derived. Through the analysis of the admittance Bode diagram, the amplitude-frequency characteristics of the three-phase converter system have conjugate symmetry in the real coordinate system and diagonal conjugate symmetry in the complex coordinate system. Therefore, the three-phase symmetrical system can be stabilized only by drawing the Nyquist curve of the open-loop transfer function GHf or GHb. The three-phase asymmetric system can also be stabilized by drawing the Nyquist curve of the modified open-loop transfer function GHfM or GHbM . Finally, the simulation results show that the converter system loses stability when the transmission line impedance Lg = 0.6 pu. In this case, the three current decoupling terms will cause the system to lose stability, but the relative stability of the current reference value is the best, and the phase angle margin is −6.8°. Also, without considering the phase-locked loop dynamics, the system is in a steady state, otherwise, the system loses stability, and the system output current has a 39 Hz oscillation, which is consistent with the theoretical analysis results.

Adaptive Delay Signal Cancellation- Synchronous Reference Frame Phase-Locked Loop Based Position Sensorless Single Stage BLDC Motor Drive for Light Duty Electric Vehicle

Adaptive Delay Signal Cancellation- Synchronous Reference Frame Phase-Locked Loop Based Position Sensorless Single Stage BLDC Motor Drive for Light Duty Electric Vehicle

Control Strategy of Three-level Active Neutral Point Clamped Grid Connected Inverters in Unbalanced Power Grid

Traditional phase-locked loops in three-level active neutral point-clamped inverter grid-connected systems for photovoltaic power generation exhibit a deficiency in the decoupling of positive and negative sequences under unbalanced power grid conditions. To address this issue, this study proposes the implementation of the fourth-order generalized integrator into the phase-locked loop to facilitate positive and negative sequence decoupling. Initially, a 3L-ANPC inverter grid connection system is established. However, under unbalanced grid voltage conditions, the PLL effect of the Decoupled Double Synchronous Reference Frame Phase-Locked Loop is found to be suboptimal, leading to considerable fluctuations and distortions in the output frequency signal. To address these complications, we propose an optimized phase-locked loop structure. In this improved design, the PLL first utilizes the FOGI to filter out multiple harmonics in the grid voltage prior to decoupling the positive and negative sequence voltage. This process effectively mitigates the effect on the PLL, thereby enabling rapid and precise tracking of the grid voltage. Simulation analysis is conducted by using Matlab/Simulink to substantiate the effectiveness of the proposed PLL, demonstrating its ability to reliably lock onto the frequency and phase of the fundamental voltage under conditions of unbalanced power grid voltage.

An Improved Dual Second-Order Generalized Integrator Phased-Locked Loop Strategy for an Inverter of Flexible High-Voltage Direct Current Transmission Systems under Nonideal Grid Conditions

High-voltage flexible power systems, with their intrinsic characteristics, play an increasingly important role in electronic power systems. Synchronization between the inverter and the grid needs to be achieved by a phase-locked loop (PLL), the performance of which determines the quality of power transmission. This paper proposes a PLL adapted to extremely harsh grid conditions. Firstly, the traditional synchronous reference frame PLL and the dual second-order generalized integrator (DSOGI-PLL) are analyzed, and the errors in phase-locking and the shortcomings of these two methods in the presence of DC components in the grid are pointed out. Secondly, based on the harmonic grid voltage, a repetitive control internal model is introduced by DSOGI to realize the real-time tracking and regulation of the harmonic signals in order to suppress the harmonic voltage disturbance. In addition, a DC bias elimination and frequency adaptive method is proposed to solve the problems of DC bias and grid voltage frequency fluctuation in order to achieve adaptive tracking of the grid phase. Finally, the superiority of the proposed strategy is verified through simulations and experiments.

A robust fusion bus frequency estimation method to improve frequency oscillation damping in power systems

AbstractThis paper proposes a new robust method for accurately and reliably estimating remote bus frequencies in a power system. Two different measurement sources for the remote bus frequency are considered, that is, the ideal Frequency Divider (FD) and the Synchronous Reference Frame Phase Locked Loops (SRF‐PLLs). Each measurement signal encounters different uncertainties and data quality issues. In this paper, both data sources are employed and fused together to better estimate the remote bus frequencies. To this end, the model structure of the power system is selected and an Unscented Kalman Filter (UKF) is utilized together with a fusion covariance intersection method to enhance the accuracy of the estimated bus frequency. Since the fusion estimation method fails in case of quality issues on both channels, a robust Generalized Maximum‐likelihood UKF (GM‐UKF) using a novel outlier detection criteria is developed. The impact of the resulting robust fusion filter on the estimation of the remote bus frequencies and on the performance of WAPSS, which makes use of the estimated frequencies as the feedback signal, is examined via simulations. The results demonstrate the excellent performance and reliability of the proposed method in dealing with noise filtering and outlier suppression while ensuring a high statistical efficiency.

Analysis of optimized phase locked loop for grid synchronization of solar PV system under grid disturbances

AbstractIn this work, an optimal phase locked loop (PLL) is employed to estimate the fundamental grid frequency and phase angle under grid disturbances, which largely reduces the frequency and phase error. Conventional synchronous reference frame (SRF) offers considerable results for balanced grid conditions but has poor performance under grid disturbances with improper phase detection. In this regard, gravitational search algorithm (GSA)‐based optimization is utilized to optimally tune the proportional and integral (PI) gain values of conventional SRF PLL, which ensures the proper tracking of fundamental phase angle and frequency even during abnormal grid conditions, that is, voltage unbalance, frequency variations, high‐frequency harmonics, and phase variations. Further, integral square error (ISE) criteria, settling time, and overshoot are considered as objective functions to obtain the optimal value of current gain, present in the control loop of a grid‐tied solar photovoltaic (PV) system. The supremacy of the proposed work, compared to SRF and optimal SRF PLL, is tested with MATLAB®/Simulink studies and verified by dSPACE‐1104‐based hardware‐in‐loop (HIL) results for real‐time validation.

Experimental Validation of a Phase Lead-Lag Synchronous Frame Phase-Locked Loop Under Different Voltage Conditions

Due to the rapid increase in single-phase inverters tied to the grid, fast and robust phase-locked loop algorithms have become indispensable. In previous work, a phase lead-lag synchronous reference frame phase-locked loop (PLL) was proposed. The method makes use of two single-tuned filters that perform as a phase detector. They are capable of shifting the phase of the grid voltage to be advanced or delayed by 45∘ with respect to the grid voltage phase. The generated orthogonal signals are transformed by Park transformation. The quadrature voltage is regulated to zero by means of a PI controller, while its output determines the frequency of the grid voltage and the phase angle obtained by integrating the estimated frequency. In this paper, deficiencies in the previous work are addressed. A small signal model of the method which takes into account frequency variation, voltage variation, and harmonic distortion is derived and presented. The design guidelines are discussed and an example illustrated. The method is validated through simulations and experiments under various voltage conditions while the algorithm is implemented on a rapid prototyping MicroLabBox. It is tested under different voltage scenarios, generated by a programmable AC source. The experimental results show that the method can track the phase angle of the grid voltage with nearly zero phase error under normal voltage conditions. It can track the phase of the grid voltage under 45∘ step phase jumps in 2.75 cycles, achieve harmonic attenuation of -15 dB under 15% third harmonic distortion, and attain an adequate phase margin near 45∘. This confirms that the method is fast and robust under adverse voltage conditions.

A Robust Forward Compensated Type-2 PLL Without DC Phase Error During Frequency Ramp for Embedded Magnetic Encoder

To achieve high performance vector control of permanent magnet synchronous machine (PMSM), high precision rotor angle is essential. Compared to traditionally used angle feedback device, e.g., encoder and resolver, the embedded magnetic encoder (EME) achieves high precision angle estimation without extra space occupation by installing several linear Hall sensors into PMSM cavity to monitor the flux leakage and rotor angle. The conventional synchronous reference frame (SRF) phase-locked loop (PLL) can extract phase and frequency from three or two Hall signals simultaneously. Although the type-2 SRF-PLL shows good robust performance against parameter variation, phase error emerges when input frequency changes. More specifically, a DC phase error appears in type-2 SRF-PLL during speed ramp stage due to insufficient order. Increase of the loop order removes the DC phase error but leads to instability risk. In this paper, a novel forward compensation (FC) module is attached on type-2 SRF-PLL to achieve phase error-free when frequency changes, where the instability risk is avoided. The effectiveness of proposed FC module is analytically and experimentally proved, where the phase error elimination, noise immunity and dynamic response are evaluated.

A mode switching based transient ride‐through phase‐locked loop

AbstractIn the case of grid voltage quality problems, the traditional phase‐locked loop (PLL) is hard to detect the accurate grid frequency and phase during the transient response, which will be detrimental to the transient synchronous stability of grid‐connected inverters. This paper proposes a mode switching based transient ride‐through PLL (TRT‐PLL), aiming to improve the transient phase‐locking performance through detection technique and mode switching. The TRT‐PLL incorporates a hybrid filter (HF), a dual‐speed detection module, and a state switch into the traditional synchronous reference frame PLL (SRF‐PLL) structure. The theoretical analysis and paradigm design of TRT‐PLL is presented in detail. Digital simulations and physical experiments are carried out for the comparisons with other existed PLL techniques. The results demonstrate that the satisfied transient performance of the TRT‐PLL has significant advantages, especially in the event of phase jumps.

An Improved HVDC Synchronous Firing Control Method Based on Order Switching and Phase Compensation

Synchronous reference frame phase-locked loop (SRF-PLL) is adopted in high-voltage direct current (HVDC) synchronous firing control to output the synchronous phase. The synchronous performance directly affects the accuracy of the firing pulse, and even affects whether the inverter can successfully commutate during AC asymmetric faults. Therefore, an improved HVDC synchronous firing control method based on order switching and phase compensation is proposed in this paper. The improved SRF-PLL has the functions of extracting the fundamental frequency positive sequence (FFPS) phase and switching the order. When the fault detection detects that a fault has occurred, PLL is converted from the second-order system to the first-order system, so as to shorten the out-of-lock time and make it quickly enter the resynchronization. Then, for the phase shift of commutation voltages caused by fault, the zero-crossing sampling method is used to detect the change of the commutation voltage phases, and the synchronous phase of each commutation voltage is compensated selectively. Finally, the improved method is tested in CIGRE HVDC benchmark model and Three Gorges-Shanghai (3GS) DC project model, respectively. The results show that the improved method has better effect on suppressing commutation failure.

Integral‐type half‐tangent phase‐locked loop for more electric aircraft grids

AbstractIn this paper, an integral‐type half‐tangent phase‐locked loop (IHTan‐PLL) is proposed for the varying‐frequency AC grids of more electric aircraft (MEA). First, the performance of the synchronous reference frame phase‐locked loop (SRF‐PLL) and half‐tangent phase‐locked loop (HTan‐PLL) is discussed from a large‐signal viewpoint. When the frequency changes largely, the SRF‐PLL has many oscillations and endures a rather long transient process. The HTan‐PLL can address the large frequency jumps. However, for the varying‐frequency AC grids with harmonic disturbances, the HTan‐PLL still has oscillations in estimating the frequency when the frequency jumps largely. To enhance the performance of the SRF‐PLL and HTan‐PLL, the IHTan‐PLL is developed for the varying‐frequency AC grids with harmonic disturbances. The IHTan‐PLL performs better than the SRF‐PLL and HTan‐PLL in addressing the large frequency jumps. Specifically, under any large frequency changes, the IHTan‐PLL still converges to the equilibrium point (0,0), and no oscillations emerge. In addition, the IHTan‐PLL has better steady‐state accuracy in estimating the frequency than the SRF‐PLL and HTan‐PLL. The experimental results also demonstrate the superior performance of the proposed IHTan‐PLL.

Hybrid AC/DC control techniques with improved harmonic conditions using DBN based fuzzy controller and compensator modules

Hybrid AC–DC microgrid provides highly distributed generation receiving capacity by reducing multiple power conversions in individual AC or DC microgrids. Thus, the control of grid variables in a hybrid AC–DC microgrid is complicated due to erroneous frequency transients and the impact of negative sequence components. Hence, a novel Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) with Self-curing decoupling network is introduced in which this network provides synchronization and distinguishes positive and negative sequences in discrete blocks. To eliminate fluctuation of grid variables in ac and dc sides, a novel Switched Tuned Arm Filter (STAF) and Variable Voltage Stabilization Compensator (VVSC) Multi-loop controller including central Deep Belief Network (DBN) with Fuzzy controller is presented. In which STAF Multi-loop controller use tuned circuits to suppress higher-order harmonics. Also, a central DBN with a fuzzy controller provides a control signal to an ac/dc converter to regulate power transmission. Additionally, in order to stabilize the dynamic voltage and compare the DC bus voltage with the reference value, the VVSC Multiloop controller uses a PWM to compare the DC bus voltage. Then the proposed techniques are simulated in Simulink platform and the results achieved stabilized voltage, low RMSE, and low delay.

An Improved Delayed Signal Cancelation for Three-Phase Grid Synchronization with DC Offset Immunity

The presence of the DC components in the grid voltage adversely affects the performance of the synchronization unit, causing oscillatory and offset errors in the estimated grid information. Several approaches were proposed to address the DC offset problem by incorporating an additional filtering stage to the synchronous reference frame phase-locked loop (SRF-PLL). Removing the DC offset using the modified delayed signal cancelation (MDSC) operator in the inner loop of the SRF-PLL shows a good DC offset elimination with a fast-dynamic response. However, neither a straightforward selection procedure for the MDSC parameters nor a general estimation technique for the grid information is provided. Hence, a generalization for the MDSC is proposed in this paper based on general mathematical expressions to cancel out the DC offset, while meanwhile estimating the grid parameters precisely and rapidly against any delay factor selection. Finally, comprehensive simulation and experimental results compared with other related PLLs are presented to demonstrate the effectiveness of the proposed work.

Presynchronization Control for Grid-Connected Inverters Without Grid Voltage Sensors

The grid voltage sensorless control for grid-connected inverters samples the line current to estimate the voltage at the point-of-common-coupling and achieve grid synchronization. The sensorless control tends to enlarge in-rush currents and fails to connect to the grid. For addressing this issue, this letter proposes a presynchronization control strategy to achieve a fast and reliable connection to the grid. By applying periodic pulses with a designed duty cycle, the converter operates in the rectifier mode with unit power factor before being connected to the ac grid as an inverter. The initial phase of the ac grid can thereby be estimated by the sampled current, where a synchronous reference frame phase-locked loop is applied to obtain the current phase. The proposed strategy is validated by experimental tests.

An enhanced phase-locked loop for non-ideal grids combining linear active disturbance controller with moving average filter

Aiming at the accuracy deterioration of the synchronous reference frame phase-locked loop (SRF-PLL) caused by the non-ideal grid conditions and the limitation of phase-locked loop based on the linear active disturbance rejection controller (LADRC-PLL), this paper proposes an enhanced three-phase phase-locked loop combining the improved moving average filter and linear active disturbance rejection controller (IMAF-LADRC-PLL). First, a linear extended state observer (LESO) is presented to estimate all uncertainties and disturbances of SRF-PLL. On this basis, an improved moving average filter (IMAF) with phase-lead compensator is used to further enhance the harmonic suppression property. By combining the LESO and IMAF in a specific control structure, the proposed IMAF-LADRC-PLL has satisfactory steady-state accuracy without sacrificing the dynamic performance. To ensure the phase-locked accuracy against frequency fluctuation, a frequency-adaptive implementation is suggested. Furthermore, the parameter tuning and performance analysis of IMAF-LADRC-PLL are also presented in this paper. Experimental results show that the proposed IMAF-LADRC-PLL can achieve better dynamic performance on frequency step response and maintain the phase-locked accuracy in the presence of grid harmonics, voltage unbalances and direct current offsets, compared with the traditional LADRC-PLL or PID-type IMAF-PLL strategy.

Optimum Setting Algorithm Based PI Controller Tuning for SRF-PLL Used Grid Synchronization System

Synchronous reference frame-phase lock loop (SRF-PLL) is most widely used for grid synchronization applications. PLL structure typically consists of a phase detector (PD), loop filter (LF) and voltage control oscillator (VCO). Design and tuning of proportional-integral (PI) controller based LF is a changeling task under distorted grid voltage conditions. Conventional tuning methods such as symmetrical optimum (SO) and Ziegler-Nichols techniques are used to tune the PI controller, resulting in increased phase margin (PM) of the system. However, high bandwidth develops harmonics in the extracted signals under non-ideal grid conditions and affects the stability. In this research article, a new optimum setting algorithm is proposed to tune the PI controller and effective synchronization is achieved. The plant is reduced as a first-order plus dead time delay (FOPDT) model and critical gain; critical frequency of the open loop system transfer function is used to model the LF of the SRF PLL system. The controller parameters are derived such that minimization of time-weighted integral performance criteria is achieved and phase angle, frequency of the grid voltage is accurately extracted. The performance of the proposed optimum setting algorithm for the SRF-PLL grid synchronization technique is discussed in detail and simulation results are presented.

A Half-Tangent Phase-Locked Loop for Variable-Frequency Grids of the More Electric Aircraft

In this article, a half-tangent phase-locked loop (HTan-PLL) is proposed for variable-frequency grids of more electric aircrafts. First, the pros and cons of the synchronous reference frame PLL (SRF-PLL) are discussed in a nonlinear framework. To address the disadvantages, a half-tangent phase detector (PD) is developed and a novel PLL is then proposed. Subsequently, a phase portrait-based analysis and a Lyapunov function-based argument are provided. It is proven that the HTan-PLL has a good performance in terms of steady-state accuracy and fast dynamics, even under large frequency changes. Compared with the conventional SRF-PLL, the proposed HTan-PLL outperforms with the following features: faster dynamics than the SRF-PLL when the frequency varies largely; no unstable equilibrium points, while the SRF-PLL has infinite unstable equilibrium points; and when the grid frequency jumps widely, the HTan-PLL converges to the unique equilibrium point (0,0). By contrast, the SRF-PLL goes to different equilibrium points. Experimental tests are provided, which verify the superior performance of the HTan-PLL.

Enhanced PLL-less grid synchronization algorithm amidst unbalanced and distorted three-phase grid conditions

Fast and precise tracking of grid voltage attributes is essential for the smooth and reliable control and operation of grid-side converters. The synchronous reference-frame phase-locked loop (SRF-PLL) approach is commonly used for this purpose, although it has issues related to the stability limit and sluggish transient response. Consequently, PLL-less grid synchronization approaches are becoming increasingly prevalent. In this context, in the present paper, a discrete Fourier transform-based band pass filter (DFT-BPF) is designed in the prefiltering stage for the purpose of extracting the fundamental frequency positive sequence component (FFPS) from unbalanced and distorted grid conditions. Despite being widely used, the SRF-PLL is struggling with stability issues and demands tedious tuning effort. For this objective, a simple frequency estimator has been developed, which is capable of accurately estimating the fundamental frequency. Additionally, a curve fitting based error correction technique is employed to adaptively estimate the amplitude and phase-angle of the fundamental component without using frequency feedback loop. The experimental results validate the efficacy of the proposed scheme.