Optimum Setting Algorithm Based PI Controller Tuning for SRF-PLL Used Grid Synchronization System

Abstract

Synchronous reference frame-phase lock loop (SRF-PLL) is most widely used for grid synchronization applications. PLL structure typically consists of a phase detector (PD), loop filter (LF) and voltage control oscillator (VCO). Design and tuning of proportional-integral (PI) controller based LF is a changeling task under distorted grid voltage conditions. Conventional tuning methods such as symmetrical optimum (SO) and Ziegler-Nichols techniques are used to tune the PI controller, resulting in increased phase margin (PM) of the system. However, high bandwidth develops harmonics in the extracted signals under non-ideal grid conditions and affects the stability. In this research article, a new optimum setting algorithm is proposed to tune the PI controller and effective synchronization is achieved. The plant is reduced as a first-order plus dead time delay (FOPDT) model and critical gain; critical frequency of the open loop system transfer function is used to model the LF of the SRF PLL system. The controller parameters are derived such that minimization of time-weighted integral performance criteria is achieved and phase angle, frequency of the grid voltage is accurately extracted. The performance of the proposed optimum setting algorithm for the SRF-PLL grid synchronization technique is discussed in detail and simulation results are presented.