Synchronous Parallel Research Articles

Circuit-size lower bounds and non-reducibility to sparse sets

As remarked in Cook (“Towards a Complexity Theory of Synchronous Parallel Computation,≓ Univ. of Toronto, 1980), a nonlinear lower bound on the circuit-size of a language in P or even in NP is not known. The best known published lower bound seems to be due to Paul (“Proceedings, 7th ACM Symposium on Theory of Computing,≓ 1975). In this paper it is shown first that for each nonnegative integer k there is a language L k in σ 2 ⌢ π 2 (of the Meyer and Stockmeyer (“Proceedings, 13th IEEE Symposium on Switching and Automata Theory,≓ 1972) hierarchy) which does not have O( n k )-size circuits. Using the same techniques, one is able to prove several similar results. For example, it is shown that for each nonnegative integer k , there is a language L k in NP that does not have O( n k )-size uniform circuits. This follows as a corollary of a stronger result shown in the paper. This result like the others to follow is not provable by direct diagonalization. It thus points to the most interesting feature of the techniques used hereby using the polynomial-time hierarchy, they are able to prove results about NP that cannot seem to proved by direct diagonalization. Finally, it is noted that existence of “small circuits≓ is in suitable contexts equivalent to being reducible to sparse sets. Using this, one is able to prove, for example, that for any time-constructible superpolynomial function f ( n ), NTIME( f ( n )) contains a language which is not many-to-one p -time reducible to any sparse set.

An MIMD parallel computer system

The need to run large, compute-bound programs encountered in research, coupled with the high availability of mini- and microcomputers in the laboratory environment, has prompted the linking of independent processors to form multicomputer systems. Important characteristics of the system presented here are the lack of shared memory between processors and the use of purely standard hardware to effect the linking. The resulting MIMD machine is suitable for executing asynchronous and weakly synchronous parallel programs. This is facilatated by assembly language software support to handle communication and to organise the independent sections of executable code for the individual processors. The design principles involved in this hardware configuration and the attendant software are introduced. A brief description of program execution behaviour is given. Applications and examples of programming problems which have been implemented on the system are discussed. An empirical method for assessing the timewise gain which ensues from use of the system is presented and experimental results obtained are outlined.

On formulating simultaneity for studying parallelism and synchronization

When studying parallel computation and synchronization one is faced with the problem of modeling the simultaneous execution of processes. Although there has been a multitude of formal means for representing such problems [2, 6, 9, 10, 13, 14, 15], invariably, when all the other complexities of the models have been stripped away, the parallelism or synchronization is studied via sequences of events. In all of these studies simultaneity of events is not studied directly. Rather, it is represented by the interleaving of the separate events into sequences, and by studying properties of the set of all such sequences.

A Study of Schedules as Models of Synchronous Parallel Computation

A Study of Schedules as Models of Synchronous Parallel Computation

Theory of data structures and synchronous parallel computations

The computational processes taking place in data-processing systems are generated at various levels of interaction between the hardware and the programs. The fundamental mathematical model used to study such processes is the composition of two systems control and information media. If each of these systems is represented in the form of an automaton, we arrive at the concept of the discrete converter [1]. The corresponding model, usually considered in the theory of programming, is an interpretational program scheme [2]. One of the important resources for raising the performance of data-processing systems is the utilization of parallel computations~ The possibility of rendering computational processes parallel is determined by the structure of the information medium, whose state is usually represented by the mapping b: R ~ D, where R is a set of memory elements (variables, registers, etc.), and D is a set of elementary values. The degree of parallelism of computational processes is defined by the intensity with which the possibilities of simultaneously changing the values of many variables are utilized.

A 53 MHz Randomly Triggered Synchronous Predetermined Scaler for Accelerator Diagnostics

A 53 MHz random triggered recycling, predetermined start-stop scaler is described. The scaler has a range from 2-to-9999 counts, sensitivity of 40 mV rms and provides both NIM and TTL standard logic outputs. The scaler is composed mainly of standard ECL integrated circuits including universal counters, configured in a synchronous parallel carry connection, and ordinary logic gates and flip-flops. Special circuitry has been designed to prevent start-up counting errors due to the phase randomness between the applied start triggering and input signal transitions. Following a start trigger, the scaler cycles until disabled, delivering an output pulse each time the predetermined count is reached. The time jitter of the output pulses with respect to the periodic input signal is less than 0.1 ns. High resolution examination of the behavior of individual charge bunches within the accelerator is made possible when the scaler is set to count the machine's harmonic number. If the scaler is set one digit away from the harmonic number, the output pulses advance one bunch for each turn around the machine, allowing a sequential display of the contents of each bucket in the machine.