Synchronous Adder Research Articles

VLSI Implementation of Heterogeneous Adder for Performance Optimization

An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power consumption. However, area and speed are two conflict parameters. So, improving speed results always in larger area occupied by circuit on chip and vice-versa. In order to design an optimized adder circuit which provides area/delay tradeoffs, we studied different available parallel, synchronous adders and proposed a new adder based on combination of them. In this paper, we proposed a new type of adder architecture known as heterogeneous adder that consists of concatenation of sub-adder (homogeneous adder) of different types. The heterogeneous adder architecture provides better design tradeoffs in terms of area and delay characteristics.

Area-time-power tradeoffs in parallel adders

In this paper, several classes of parallel, synchronous adders are surveyed based on their power, delay and area characteristics. The adders studied include the linear time ripple carry and Manchester carry chain adders, the square-root time carry skip and carry select adders, the logarithmic time carry lookahead adder and its variations, and the constant time signed-digit and carry-save adders. Most of the research in the last few decades has concentrated on reducing the delay of addition. With the rising popularity of portable computers, however, the emphasis is on both high speed and low power operation. In this paper we adopt a uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion. The relative merits of the different adders are evaluated by performing a detailed transistor-level simulation of the adders using HSPICE. Among the two's complement adders, a variation of the carry lookahead adder, called ELM, was found to have the best power-delay product. Based on the results of our experiments, a large adder design space is formulated from which an architect can choose an adder with the desired characteristics.

Design for a multi-input binary adder

The need often arises in digital systems for a fast multi-input adder capable of adding together n distinct serial binary numbers. The normal design method is to employ a parallel-series configuration of 2-input synchronous adders. It is shown how the overall speed of a multi-input adder may be enhanced using a 3-input adder stage. A circuit is described using cascaded 2- and 3-input synchronous adders, which may be clocked at 100 ns allowing the addition of six 10-bit binary numbers in lµs.