Symmetrical Threshold Voltages Research Articles

Threshold Voltage Adjustment on 4H-SiC MOSFETs Using P-Doped Polysilicon as a Gate Material

To scale digital circuits, symmetric threshold voltages (Vth) for n-type transistors (NMOS) and p-type transistors (PMOS) are important. One step towards this in silicon carbide (SiC) is selecting a p-doped polysilicon (pPolySi). This implementation has been shown in this work with Vth being evaluated by five different methods. Furthermore, operating temperatures up to 500 °C and their impact on Vth were investigated. It has been successfully demonstrated that elevated temperature shifts Vth of both transistor types towards 0 V, whereas changing the gate electrode from n-doped PolySi (nPolySi) to pPolySi shifts Vth of both transistor types to more positive values. Both effects are complementary for the PMOS, reaching Vth below 4 V.

Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and Balanced Driving Currents Using Single Work Function Metal Process

In this article, one feasible fabrication approach for novel fishbone FETs using the channel-first and single work function metal (sWFM) processes is proposed and investigated by 3-D technical computer-aided design (TCAD) simulations. Through a small modification on the fabrication process of general gate-all-around (GAA) nanosheet FETs (NSFETs), the special fishbone-like channel composed of vertically stacked Si NSs and sandwiched SiGe nano-fins is experimentally demonstrated by the channel-first process. The simulated electrical characteristics show that the width of the nano-fins should be within 5 nm for a better gate control. Unlike traditional NSFETs, symmetrical threshold voltages ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}\text{s}$ </tex-math></inline-formula> ) for n-type and p-type fishbone FETs can be achieved by using a sWFM, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta {V}_{\text {th}}$ </tex-math></inline-formula> is optimized by 99.26% compared with that of NSFETs. Meanwhile, it is also found that the SiGe nano-fins contribute more driving current for p-type devices. Therefore, the proposed fishbone FETs with sWFM not only exhibit significantly enhanced driving current but also provide good balance between the performances of n-type and p-type fishbone FETs with a little extra process cost.

Formation of carbon films as the subgate dielectric of GaAs microcircuits on Si-substrates

The technological aspects of the formation of thin α-C:H carbon films, the peculiarities of the ion-plasma Q-DLTS spectra of heterostructures α-C:H-Si and α-C: H-GaAs are considered, and activation energy, cross-trapping and density of deep traps, responsible for charge state, are determined. The correlation between the technological regimes of the α-C:H film formation and trap density is established. The technological methods and regimes that allow obtaining structures with a relatively small surface state density N ss ≤10 12 cm -2 are determined. This allows using these structures as a subgate dielectric in GaAs-CMOS structures of LSICs. Low-temperature epitaxy of GaAs-layers on silicon substrates with the use of excimer lasers is developed, where germanium film acts as a buffer layer between Si and GaAs. The technology of carbon films formation by deposition from the carbon target is developed. The use of carbon films as a subgate dielectric allows the formation of CMOS-transistors on GaAs-epilayers with symmetric threshold voltages, which opens a new direction for the development of the sub-micron technology of LSICs and enables to increase the LSICs speed and reduce their production cost.

Nanowatt power operation of silicon nanowire NAND logic gates on bendable substrates

In this paper, we propose a novel construction of silicon nanowire (SiNW) negative-AND (NAND) logic gates on bendable plastic substrates and describe their electrical characteristics. The NAND logic gates with SiNW channels are capable of operating with a supply voltage as low as 0.8 V, with switching and standby power consumption of approximately 1.1 and 0.068 nW, respectively. Superior electrical characteristics of each SiNW transistor, including steep subthreshold slopes, high Ion/off ratio, and symmetrical threshold voltages, are the major factors that enable nanowatt-range power operation of the logic gates. Moreover, the mechanical bendability of the logic gates indicates that they have good and stable fatigue properties.

Low-power functionality of silicon-nanowire-assembled inverters on bendable plastics

In this paper, we demonstrate the low-power functionality of silicon nanowire (SiNW)-assembled inverters on bendable plastics. Our bendable inverters are capable of operating at supply voltages as low as 0.8 V with a switching (or standby) power consumption of ∼0.2 nW (or ∼6.6 pW). The low-power inverting operation with a voltage gain of ∼18 is attributable to the near-ideal characteristics of the component transistors that have selectively thinned SiNW channels and exhibit low, symmetrical threshold voltages of 0.40 and −0.39 V and low sub-threshold swing values of 81 and 65 mV/dec. Moreover, mechanical bendability reveals that the inverting operation has good, stable fatigue properties.

Subnanowatt Carbon Nanotube Complementary Logic Enabled by Threshold Voltage Control

In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.

Low Voltage-Driven CMOS Circuits Based on SiOG

The fabrication of the low voltage-driven inverter, ring oscillator, and shift resistor using n- and p-channel thin-film transistors (TFTs) based on the silicon-on-glass (SiOG) substrate was studied. The manufacturing process of n- and p-channel TFTs was the same as that of low temperature poly-Si. The field-effect mobilities of n- and p-channel TFTs fabricated in SiOG are 226 and , respectively. The TFTs exhibited a symmetric threshold voltage of and a gate voltage swing of . The total propagation delay time of the complementary metal oxide semiconductor (CMOS) inverter was at a supply voltage of . In addition, the rise and fall times of the shift register were found to be 0.5 and at a of , respectively.

Low Voltage Driven CMOS Circuits Based on Silicon on Glass

Low voltage driven inverter, ring oscillator and shift resistor using n- and p- channel TFTs based on Corning® silicon-on-glass substrates (SiOG) is studied. The field effect mobility of n- and p-channel TFTs based on SiOG are 226 cm2/V s and 165 cm2/V, respectively. TFTs exhibit the symmetric threshold voltage of ± 1.1 V and gate voltage swing of 0.21 ~ 0.23 V/dec. The total propagation delay time of the CMOS inverter is 2.54ns at the supply voltage of 7 V. In addition, the rise and fall times of the shift register are found to be 0.5 µs and 0.7 µs at VDD of 7 V, respectively. Therefore, high performance integrated circuits can be possible on SiOG using CMOS technologies.

A New SiGeC Vertical MOSFET: Single-device CMOS (SD-CMOS)

AbstractA new type of silicon-based Vertical MOSFET concept is presented - Single-Device CMOS (SD-CMOS) - in which the same structure can be operated as NFET or as PFET, depending on the biasing conditions [1]. SD-CMOS offers new possibilities for CMOS integration schemes that are simpler - requiring only 5 masks for the “Front- End” - and less costly to manufacture, than any integration scheme requiring the fabrication of two devices with opposite polarities.In epitaxially grown Vertical MOSFETs, the source, channel and drain can have atomically sharp interfaces, well controlled doping, and channel length controlled by the epitaxial process rather than by lithography and ion-implantation. With epitaxial growth, it is straightforward to do bandgap engineering by incorporating films such as Si1-xGex, and/or Si1-yCy and/or Si1-x-yGexCy, into any of the aforementioned regions. Suitable band offsets at the source/channel interface [2] can suppress DIBL, which is a key limitation to CMOS scaling. These advantages of Vertical MOSFETs are crucial for future CMOS technology nodes, such as 22nm and below.SD-CMOS has a metallic drain region with work-function close to the mid-gap energy of the channel material, which can be a homogenous material, a random alloy, or a superlattice. The source region has a very narrow bandgap, achievable with (Si1-yCy)m-(Si1-xGex)n superlattices, whose mid-gap level is aligned with that of the channel region, and with band offsets with the channel region that are nearly symmetric for the conduction and valence bands. The source contact is a metal with a work-function close to the mid-gap level of the source and channel regions, which in turn are aligned with the work-function of the drain. The potential barrier, for electrons and holes from the source contact to the source region, is required to be just a few KT. For operation as NMOS and PMOS with nearly symmetric threshold voltages, the work-function of the gate electrode is also aligned with the mid-gap energy level of the channel.SD-CMOS is unique due to its band alignments: symmetric band edges, from source to drain, with respect to the mid-gap energy (the “mirror” line). Such configuration can only be obtained in the absence of doping, which if present would immediately break that symmetry. The conduction and valence band edges are required to be asymmetric with respect to a cross-section line crossing the channel through the middle of the gate.The conduction (valence) band offset between source and channel sets the barrier height for electrons (holes) in the OFF condition for NMOS (PMOS), while applying a voltage at the gate leads to the accumulation of electrons (holes) at the source/channel interface, thereby pushing the Fermi-Level in the source above (below) the conduction (valence) band edge of the channel for the ON condition. Band diagrams and a CMOS fabrication flow for SD-CMOS will be presented. [1] US Patent 6,674,099 [2] US Patent 5,914,504

Quasi-damascene metal gate/high- k CMOS using oxygenation through gate electrodes

We present a novel metal gate/high- k complementary metal–oxide–semiconductor (CMOS) integration scheme with symmetric and low threshold voltage ( V th) for both n-channel (nMOSFET) and p-channel (pMOSFET) metal–oxide–semiconductor field-effect transistors. The workfunction of pMOSFET is modulated by oxygen in-diffusion (‘oxygenation’) through the titanium nitride metal gate without equivalent oxide thickness (EOT) degradation. A significant V th improvement by 420 mV and an aggressively scaled capacitance equivalent thickness under channel inversion ( T inv) of 1.3 nm is achieved for the pFET by using a replacement process in conjunction with optimized oxygenation process. Immunity of nMOSFET against oxygenation process is demonstrated.

Dual-Metal-Gate Transistors with Symmetrical Threshold Voltages Using Work-Function-Tuned Ta/Mo Bilayer Metal Gates

We have investigated dual-work-function metal gates based on Mo and stacked Ta/Mo fabricated by an interdiffusion method that does not require a metal etching process from the gate dielectrics. The diffusion of Ta into the Mo layer provides a markedly reduced work function for the Ta/Mo gate (4.42 eV) in comparison with that for the single Mo gate (5.04 eV). The metal–oxide–semiconductor field-effect transistors (MOSFETs) with the Mo and Ta/Mo gates on 4-nm-thick SiO2 were fabricated by the gate-first process with dopant activation annealing at 850 °C. The Ta/Mo-gate n-MOSFET with the reduced gate work function and the Mo-gate p-MOSFET exhibited almost symmetrical threshold voltages (+0.53/-0.45 V). It was also confirmed that the Ta/Mo interdiffusion process did not degrade the gate dielectric integrity and electron mobility in contrast to the case of the single Mo gate.

Low voltage and low power embedded 2T-SONOS flash memories improved by using P-type devices and high- K materials

16 Mb 2-transistor (2T)-SONOS flash memories have been processed in a 0.18 μm CMOS technology. The 2T NOR architecture allows fast random access and low power program and erase by tunneling. Also, negative erased threshold voltages enable low voltage read without boosting. This paper shows the operation and reliability aspects of 2T N-type SONOS memories: endurance, retention and read disturb. A further reduction in read voltage is demonstrated by using P-type SONOS and makes it even possible to operate the devices with a symmetric threshold voltage ( V T) window around 0 V. In this case, read disturb is completely avoided and the advantages of the 2T NOR architecture are fully used, meaning fast random access and real low power operation. Besides SONOS embedded flash memories, also the reliability of devices with either the top layer or trapping layer made of the high- K materials HfO 2 or HfSiON have been investigated. The memories with a high- K top layer are indicated by SHINOS (Silicon-High- K-Nitride-Oxide-Silicon). A strong gain in program/erase efficiency can be obtained for SHINOS compared with SONOS memories. The SHINOS devices show good endurance and retention. The retention of the SHINOS devices can be considerably improved by trading-off the improved program/erase efficiency with a thicker bottom oxide.

High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

Dual metal gate transistors with high-k gate dielectrics have been investigated for low-power metal oxide semiconductor (MOS) devices in 45 nm nodes and beyond. Using high-quality HfSiO gate dielectrics, using TiN and Ta for the gate electrode, and minimizing process damage, we have succeeded in markedly improving device performance. Effective work functions of 4.9 eV for TiN and 4.3 eV for Ta on HfSiO were obtained for the first time. Symmetrical threshold voltages of ±0.5 V were realized for these work functions. Small hysteresis and low interface trap densities for both TiN and Ta were obtained, which are almost the same as those of poly-Si/HfSiON transistors. No degradation in electron mobility was achieved for the first time for Ta-NMOS transistors at an effective field of 1.0 MV/cm. The gate leakage current at an equivalent electrical oxide thickness in an inversion of 1.7 nm was suppressed to 1 mA/cm-2 at a gate bias of Vth+0.6 V.

Characterization of the Ultrathin Vertical Channel CMOS Technology

In this paper, an ultrathin vertical channel (UTVC) CMOS with self-aligned asymmetric lightly doped drain is experimentally demonstrated. In the structure, the UTVC was obtained using solid phase epitaxy, and the midgap material, boron-doped poly-Si/sub 0.5/Ge/sub 0.5/, was used as the gate electrode to obtain symmetrical threshold voltages for both the NMOS and PMOS devices. Due to the ultrathin channel, the fabricated CMOS devices offer good immunity to short channel effects, and the typical subthreshold slopes of the 80 nm NMOS and PMOS are 102 mV/dec and 120 mV/dec, respectively. The fabricated CMOS inverters also show reasonable transfer characteristics. The UTVC CMOS technology provides a simple way to implement sub-100 nm devices for ULSI applications.

Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology

We present the design, fabrication and characterization of fully depleted silicon on insulator (FDSOI) CMOS devices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 μm, 2-input NAND gate FDSOI CMOS ring oscillators. Polysilicon gate depletion and source–drain series resistance limit the performance of the FDSOI CMOS technology. A simplified model combined with high frequency capacitance–voltage measurements at two different frequencies is developed to determine the series resistance and polysilicon gate depletion effects.