Symmetric Multiprocessor Research Articles

Practical algorithms for scheduling video data in a local area network environment

Simultaneous transmission of multiple high quality video streams from a server to the clients is becoming an increasingly important class of traffic in a network of workstations or cluster environment. With a powerful symmetric multiprocessor (SMP) as the server and a high-speed network, such transmission is practicable from a hardware point of view. However, the actual construction of such a video data server system entails tackling a number of difficult problems related to the provision of strict quality of service (QoS) guarantees. Among others, the smoothing and scheduling of multiple video packet streams are two crucial issues. Smoothing is concerned with reducing the rate variability of video streams in view of the fact that video data are usually compressed in a variable bit rate fashion. Scheduling is important to guarantee the requested QoS levels while maximizing the utilization of the resources. Although much work on smoothing has been done, it is not clear which scheduling scheme is suitable for multiplexing smoothed video data to the network. In this paper we present an extensive performance study of the EDF and RM scheduling algorithms which are modified to provide QoS guarantees for smoothed video data. With a probabilistic definition of QoS, admission control conditions are incorporated into the two algorithms. Furthermore, a counter-based scheduling module is included as the core scheduling mechanism which adaptively adjusts the actual QoS levels assigned to requests. Our theoretical analysis of the two modified algorithms, called QEDF and QRM, shows that the QRM algorithm is more robust than the QEDF algorithm for different workload and utilization conditions. We also propose to use a new metric called meta-QoS to quantify the overall performance of a packet scheduler given a set of simultaneous requests. In our experiments based on an SMP-based Linux platform, we find that the QRM algorithm can sustain a rather stable level of meta-QoS even when the workload and utilization levels are increased. On the other hand, the QEDF algorithm, due to its conservative admission control policy, is found to be not suitable for a high level of utilization and a large number of requests. In view of the lower complexity of the QRM algorithm, it seems that the QRM approach is a more suitable candidate for packet scheduling in the client-server environment considered in our study.

Parallel Implementations of 1-D Fast Fourier Transform Without Interprocessor Communication

Computing 1-D Fast Fourier Transform (FFT ) using the conventional 4-step FFT on parallel computers requires intensive all-toall communication, which can adversely affect the performance of FFT. In this paper, we present 2-step-no-communication and 3-step-no-communication algorithms, which are parallel algorithms for 1-D FFT without interprocessor communication. One of the main advantages of these algorithms is the absence of all-to-all communication between processors, albeit at the expense of increased computation compared to the conventional 4-step FFT. If the cost of extra computation required by the 2-step-no-communication and the 3-step-no-communication algorithms is more than offset by the cost of all-to-all communication in the 4-step FFT , then these two no-communication algorithms will outperform the 4-step FFT algorithm. We test the 2-step-no-communication and the 3-step-nocommunication algorithms in two parallel systems (a 32-node Beowulf cluster and 8-node symmetric multiprocessors), with varying costs of all-to-all communication and computation. The experimental results show that the no-communication algorithms perform better than the 4-step FFT in the SMP only for relatively small data sizes, but the no-communication algorithms outperform the 4-step FFT in the Beowulf cluster for all data sizes tested.

Stabilizing large‐scale generalized systems on parallel computers using multithreading and message‐passing

AbstractWe discuss the parallelization of an efficient algorithm for the partial stabilization of large‐scale linear control systems in generalized state‐space form. The algorithm is composed of highly parallel iterative schemes that appear in the computation of certain matrix functions. Here we evaluate different approaches to exploit parallelism at two levels, based on threads and processes. Our experimental results on a cluster of symmetric multiprocessors and a CC‐NUMA platform show that the efficiency of the matrix operations underlying the iterative schemes carry over to the parallel implementation of the stabilization algorithm. Copyright © 2006 John Wiley & Sons, Ltd.

STORM: Scalable Resource Management for Large-Scale Parallel Computers

Although clusters are a popular form of high-performance computing, they remain more difficult to manage than sequential systems - or even symmetric multiprocessors. In this paper, we identify a small set of primitive mechanisms that are sufficiently general to be used as building blocks to solve a variety of resource-management problems. We then present STORM, a resource-management environment that embodies these mechanisms in a scalable, low-overhead, and efficient implementation. The key innovation behind STORM is a modular software architecture that reduces all resource management functionality to a small number of highly scalable mechanisms. These mechanisms simplify the integration of resource management with low-level network features. As a result of this design, STORM can launch large, parallel applications an order of magnitude faster than the best time reported in the literature and can gang-schedule a parallel application as fast as the node OS can schedule a sequential application. This paper describes the mechanisms and algorithms behind STORM and presents a detailed performance model that shows that STORM's performance can scale to thousands of nodes

High performance noise reduction for biomedical multidimensional data

Anisotropic nonlinear diffusion (AND) is one of the most powerful noise reduction techniques in the field of image processing. This method is based on a partial differential equation (PDE) tightly coupled with a massive set of eigensystems. Denoising large 3D images in biomedicine and structural cellular biology by AND is extremely expensive from a computational point of view, with huge memory needs. In this work, high performance computing techniques have been applied to AND. An strategy for optimal memory usage has been designed, which has allowed a remarkable reduction of the memory requirements. Parallel implementations of AND have been developed with special focus on clusters of symmetric multiprocessors (SMPs), currently a dominant platform in high performance computing. Different programming models have been used for the parallelization of AND: (1) Message-passing paradigm using MPI and (2) a hybrid paradigm that uses message passing among nodes plus the shared address space paradigm between the processors within the nodes. The parallel approaches have been evaluated on a cluster of dual-Xeon nodes, a representative example of clusters of SMPs. The conclusion drawn is that the hybrid approach is the most suitable for the parallelization of AND for this kind of computing platforms.

On Parallelization of a Spatially-Explicit Structured Ecological Model for Integrated Ecosystem Simulation

Spatially explicit landscape population models are widely used to analyze the dynamics of an ecological species over a realistic landscape. These models may be data intensive applications when they include the age and size structure of the species in conjunction with spatial information coming from a geographic information system (GIS). We report on parallelization of a spatially explicit landscape model (PALFISH), in a component-based simulation framework, utilizing different parallel architectures. A multithreaded programming language (Pthread) is used to deliver high scalability on a symmetric multiprocessor (SMP), and a message-passing library is deployed for parallel implementation on both an SMP and a commodity cluster. The PALFISH model delivers essentially identical results as a sequential version but with high scalability: yielding a speedup factor of 12 as the runtime is reduced from 35 hours (sequential ALFISH) to 2.5 hours on a 14processor SMP. Hardware performance data were collected to better characterize the parallel execution of the model on the different architectures. This is the first documentation of a high performance application in natural resource management that uses different parallel computing libraries and platforms. Due to the diverse needs for computationally intensive multimodels in scientific applications, our conclusions arising from a practical application which brings the software component paradigm to highperformance scientific computing, can provide guidance for appropriate parallelization approaches incorporating multiple temporal and spatial scales.

CuPIDS: An exploration of highly focused, co-processor-based information system protection

The Co-Processing Intrusion Detection System (CuPIDS) project explores improving information system security through dedicating computational resources to system security tasks in a shared resource, multi-processor (MP) architecture. Our research explores ways in which this architecture offers improvements over the traditional uni-processor (UP) model of security. One approach we examined has a protected application running on one processor in a symmetric multi-processing (SMP) system while a shadow process specific to that application runs on a different processor. The shadow process monitors the application process' activity, ready to respond immediately if the application violates policy. Experiments with a prototype CuPIDS system demonstrate the feasibility of this approach in the context of a self-protecting and self-healing system. An untuned prototype supporting fine-grained protection of the real-world application WU-FTP resulted in less than a 15% slowdown while demonstrating CuPIDS' ability to quickly detect illegitimate behavior, raise an alarm, automatically repair the damage done by the fault or attack, allow the application to resume execution, and export a signature for the activity leading up to the error.

Application of information system technologies to power control centers in a liberalized environment

AbstractThis paper describes the new control centers that are incorporated with information system technologies to handle precise security margins on a wide level and secure information exchange between system operators and other actors emerging in the liberalized electric power supply environment in progress. To further realize the system stress analysis by high‐speed processing, symmetric multi processor (SMP) servers are adopted through cost‐effective performance from the standpoint of investment protection. The performance improvements and observations are shown with processing time measurements according to the peculiarity of the power system analysis software packages embedded in the client‐server‐based energy management system (EMS). To cope with malicious intrusions into the cyber space through data links with outside information systems, an information exchange method using tough Internet protocol (IP) separation between information system and control system portions is also presented using a practical example, with cyber security strictly maintained among the other internal information systems in an electric power utility. © 2006 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

A Transparent Distributed Shared Memory for Clustered Symmetric Multiprocessors

A transparent distributed shared memory (DSM) system must achieve complete transparency in data distribution, workload distribution, and reconfiguration respectively. The transparency of data distribution allows programmers to be able to access and allocate shared data using the same user interface as is used in shared-memory systems. The transparency of workload distribution and reconfiguration can optimize the parallelism at both the user-level and the kernel-level, and also improve the efficiency of run-time reconfiguration. In this paper, a transparent DSM system referred to as Teamster is proposed and is implemented for clustered symmetric multiprocessors. With the transparency provided by Teamster, programmers can exploit all the computing power of the clustered SMP nodes in a transparent way as they do in single SMP computer. Compared with the results of previous researches, Teamster can realize the transparency of cluster computing and obtain satisfactory system performance.

Fast shared-memory algorithms for computing the minimum spanning forest of sparse graphs

Minimum spanning tree (MST) is one of the most studied combinatorial problems with practical applications in VLSI layout, wireless communication, and distributed networks, recent problems in biology and medicine such as cancer detection, medical imaging, and proteomics, and national security and bioterrorism such as detecting the spread of toxins through populations in the case of biological/chemical warfare. Most of the previous attempts for improving the speed of MST using parallel computing are too complicated to implement or perform well only on special graphs with regular structure. In this paper we design and implement four parallel MST algorithms (three variations of Borůvka plus our new approach) for arbitrary sparse graphs that for the first time give speedup when compared with the best sequential algorithm. In fact, our algorithms also solve the minimum spanning forest problem. We provide an experimental study of our algorithms on symmetric multiprocessors such as IBMs pSeries and Sun's Enterprise servers. Our new implementation achieves good speedups over a wide range of input graphs with regular and irregular structures, including the graphs used by previous parallel MST studies. For example, on an arbitrary random graph with 1 M vertices and 20 M edges, our new approach achieves a speedup of 5 using 8 processors. The source code for these algorithms is freely available from our web site.

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%

A Parallel Fish Landscape Model for Ecosystem Modeling

Parallelization of a landscape fish population model (ALFISH) is an important effort towards high performance Across Tropic Level System Simulation (ATLSS) on a computing grid. ALFISH models the impacts of different water management strategies in the South Florida region on the freshwater fish population, providing estimates of the food resource available to wading birds. The parallel ALFISH model delivers similar results to those from a sequential implementation. Compared with the average simulation time of the sequential model, which is about 35 hours, the speed improvement of the parallel model on a symmetric multiprocessor (SMP) is substantial. Using 14 processors, the runtime of the parallel model with static partitioning is less than 4 hours, and that of the parallel model with dynamic load balancing is less than 3 hours.

OpenMP extension to SMP clusters

This article discusses the approaches to apply the OpenMP programming model to symmetric multiprocessor (SMP) clusters using software distributed shared memory (SDSM). The major focus of this article is on the challenges that the prior studies faced and on their solution techniques. Exploiting message-passing primitives explicitly for the openMP synchronization and work-sharing directives enables light interprocess synchronizations. The studies on loop scheduling for SMP clusters will promise significant improvement in system performance. Finally, OpenMP is considered as promising programming model

Domain cloning for a particle-in-cell (PIC) code on a cluster of symmetric-multiprocessor (SMP) computers

In 2000, a new approach to parallelization, domain cloning, was presented by [C.C. Kim, S.E. Parker, Massively parallel three-dimensional toroidal gyrokinetic flux-tube turbulence simulation, Journal of Computational Physics 161 (2000) 589–604]. Domain cloning is an additional layer of parallelization, a supplement to one-dimensional domain decomposition which gives the opportunity to optimize the scaling properties of certain particle-in-cell codes. A further adaptation to a cluster of symmetric-multiprocessor computers is presented in this work. Hence, very good scaling properties up to 2048 processors could be achieved for a particle-in-cell code surpassing the Tflop/s performance threshold.

High-End Server System Partitioning for Cost Reduction

In this paper, we demonstrate the use of finite-dimension linear programming to maximize the number of partial good multicore processor chips in a symmetric multiprocessing (SMP) node of a given logical size and physical footprint. It is asserted that to the first order the cost of a productized processor chip will be proportional to the scrap of a processor chip containing good cores but being unusable for the implementation of an SMP node. Therefore, the tradeoff between the number of processing units (PUs) on a chip and the total number of PUs on an SMP node is examined. This paper shows that an optimized SMP offering can be found so that the total chip cost of a high-end system can be minimized. However, such cost reduction will limit the SMP node size for a given processor chip yield. It will also be shown that as the chip yield improves the SMP node size that can be profitably implemented will increase.

A Simple Cache Emulator for Evaluating Cache Behavior for SMP Systems

Every modern CPU uses a complex memory hierarchy, which consists of multiple cache memory levels. It is very difficult to predict the behavior of this hierarchy for a given program (for details see [1, 2]). The situation is even worse for systems with a shared memory. The most important example is the case of SMP (symmetric multiprocessing) systems [3]. The importance of these systems is growing due to the multi-core feature of the newest CPUs.The Cache Emulator (CE) can simulate the behavior of caches inside an SMP system and compute the number of cache misses during a computation. All measurements are done in the “off-line” mode on a single CPU. The CE uses its own emulated cache memory for an exact simulation. This means that no other CPU activity influences the behavior of the CE. This work extends the Cache Analyzer introduced in [4].

Task Pool Teams: a hybrid programming environment for irregular algorithms on SMP clusters

Clusters of symmetric multiprocessors (SMPs) are popular platforms for parallel programming since they provide large computational power for a reasonable price. For irregular application programs with dynamically changing computation and data access behavior, a flexible programming model is needed to achieve efficiency. In this paper we propose Task Pool Teams as a hybrid parallel programming environment to realize irregular algorithms on clusters of SMPs. Task Pool Teams combine task pools on single cluster nodes by an explicit message passing layer. They offer load balance together with multi-threaded, asynchronous communication. Appropriate communication protocols and task pool implementations are provided and accessible by an easy-to-use application programmer interface. As application examples we present a branch and bound algorithm and the hierarchical radiosity algorithm. Copyright © 2006 John Wiley & Sons, Ltd.

On the performance of parallel implementations of an ADI scheme for parabolic PDEs on shared and distributed memory systems

In this paper we present two parallel programming approaches to solving parabolic partial differential equations with mixed derivative terms using Alternating Direction Implicit (ADI) schemes. The first approach uses the multithreading technique and is suitable for use on Symmetric Multiprocessing (SMP) machines. The second approach uses multiple processes and the Message Passing Interface (MPI) for interprocess communications. Our primary interest is focused on the performance of our implementations on different platforms. For comparison, we provide performance test results using both approaches.

Efficient Adaptive Algorithms for Transposing Small and Large Matrices on Symmetric Multiprocessors

Matrix transpose in parallel systems typically involves costly all-to-all communications. In this paper, we provide a comparative characterization of various efficient algorithms for transposing small and large matrices using the popular symmetric multiprocessors (SMP) architecture, which carries a relatively low communication cost due to its large aggregate bandwidth and low-latency inter-process communication. We conduct analysis on the cost of data sending / receiving and the memory requirement of these matrix-transpose algorithms. We then propose an adaptive algorithm that can minimize the overhead of the matrix transpose operations given the parameters such as the data size, number of processors, start-up time, and the effective communication bandwidth.

Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial phases of multithreaded programs on large high-performance cores whereas parallel phases are executed on a mix of large and many small simple cores. Theoretical analysis reveals a performance upper bound for symmetric multiprocessors, which is surpassed by asymmetric configurations at certain power ranges. Our emulations show that asymmetric multiprocessors can reduce power consumption by more than two thirds with similar performance compared to symmetric multiprocessors