Symmetric Multiprocessor Research Articles

Automatic selection of high-order transformations in the IBM XL FORTRAN compilers

The IBM ASTI optimizer provides the foundation for high-order transformations and automatic shared-memory parallelization in the latest IBM XL FORTRAN (XLF) compilers for RS/6000™ and PowerPC® uniprocessors and symmetric multiprocessors (SMPs), and for automatic distributed-memory parallelizationin the IBM XL High-Performance FORTRAN (XLHPF) compiler for the SP2™ distributed-memory multiprocessor. In this paper, we describe how the transformer component of the ASTI optimizer automatically selects high-order transformations for a given input program and a target uniprocessor, so as to improve utilization of the memory hierarchy (including cache and registers) and instruction-level parallelism. Our solution is centered on a quantitative approach in which optimization problems are formulated using quantitative cost models. The loop and data transformations currently employed by the ASTI transformer for optimizing uniprocessor performance are loop distribution, loop interchange, loop reversal, loop skewing, loop tiling/blocking (with compiler-selected tile sizes), loop fusion, unrolling of multiple loops (with compiler-selected unroll factors), and scalar replacement of selected array references. The design and initial implementation of the ASTI optimizer were completed during the 1991-1993 time period. To the best of our knowledge, the ASTI transformer is the first system to perform automatic selection of this wide range of transformations using a cost-based framework.

Reinventing the supercomputer center at NERSC

The next generation of symmetric multiprocessors will add another level of memory hierarchy and new barriers to effective use of supercomputers. Helping scientists overcome such barriers to using high-performance computers was a key objective in the relocation of the National Energy Research Scientific Computing Center (NERSC) to Ernest Orlando Lawrence Berkeley National Laboratory. The relocation makes it easier for NERSC to collaborate closely with scientists at Berkeley Lab and throughout the energy research community, with scientists at the adjacent University of California's Berkeley campus, and with major computer and data communications companies throughout the San Francisco Bay area.

Scheduling multiple queries in symmetric multiprocessors

Traditionally, queries submitted to a database management system are optimized one at a time. However, queries posed to a database usually access some common relations, or share some common intermediate results. Exploiting such sharings can effectively improve the performance of the system. In this paper, we describe our approach to scheduling a group of queries for processing in symmetric multiprocessors. The novel feature of our approach is that we exploit sharings of (base) relations and/or common intermediate results for pipelined plans. We propose an optimization framework that exploits such sharings. Two scheduling algorithms are derived from the framework. The first algorithm, SerialShare, generates a serial plan, while the second algorithm, MultiShare, generates a parallel plan. An analytical model is developed to study the performance of the algorithms. Compared to the traditional method of executing one query after another without sharing, our results show that our proposed algorithms can provide significant performance improvement.

Coir: An Object-Oriented System for Control and Dynamic Data Parallelism

Parallelism in modern machines ranges from desk-tops to teraflops. It starts at the level of workstations, which are being increasingly designed as symmetric multiprocessors (SMPs), and scales up to large-scale distributed memory machines whose individual nodes are SMPs. On the software side, object-oriented and multithreading paradigms are both becoming important in software development for high-performance computing. Multithreading techniques have been used at the hardware and the operating system level to interleave computation and to overlap computation with other operations such as communication, I/O, and resource management. Lately, providing multithreading at the level of libraries and application programs has generated much interest. In this paper, we describe a system namedCoirthat combines the important aspects of multithreading with object-oriented paradigms in C++ to model the two important aspects of parallel programming—control and data-parallelism. The system provides parallelism as a C++ library and models a wide range of machines from small-scale symmetric multiprocessors to large-scale distributed address space message-passing machines.

High-performance computing — an overview

An overview of high-performance computing (HPC) is given. Different types of computer architectures used in HPC are discussed: vector supercomputers, high-performance RISC processors, various parallel computers like symmetric multiprocessors, workstation clusters, massively parallel processors. Software tools and programming techniques used in HPC are reviewed: vectorizing compilers, optimization and vector tuning, optimization for RISC processors; parallel programming techniques like shared-memory parallelism, message passing and data parallelism; and numerical libraries.

Scalable parallel computers for real-time signal processing

We assess the state-of-the-art technology in massively parallel processors (MPPs) and their variations in different architectural platforms. Architectural and programming issues are identified in using MPPs for time-critical applications such as adaptive radar signal processing. We review the enabling technologies. These include high-performance CPU chips and system interconnects, distributed memory architectures, and various latency hiding mechanisms. We characterize the concept of scalability in three areas: resources, applications, and technology. Scalable performance attributes are analytically defined. Then we compare MPPs with symmetric multiprocessors (SMPs) and clusters of workstations (COWs). The purpose is to reveal their capabilities, limits, and effectiveness in signal processing. We evaluate the IBM SP2 at MHPCC, the Intel Paragon at SDSC, the Gray T3D at Gray Eagan Center, and the Gray T3E and ASCI TeraFLOP system proposed by Intel. On the software and programming side, we evaluate existing parallel programming environments, including the models, languages, compilers, software tools, and operating systems. Some guidelines for program parallelization are provided. We examine data-parallel, shared-variable, message-passing, and implicit programming models. Communication functions and their performance overhead are discussed. Available software tools and communication libraries are also introduced.

STiNG

"STiNG" is a Cache Coherent Non-Uniform Memory Access (CC-NUMA) Multiprocessor designed and built by Sequent Computer Systems, Inc. It combines four processor Symmetric Multi-processor (SMP) nodes (called Quads), using a Scalable Coherent Interface (SCI) based coherent interconnect. The Quads are based on the Intel P6 processor and the external bus it defines. In addition to 4 P6 processors, each Quad may contain up to 4 GBytes of system memory, 2 Peripheral Component Interface (PCI) busses for I/O, and a Lynx board. The Lynx board provides the datapath to the SCI-based interconnect and ensures system-wide cache coherency. STiNG is one of the first commercial CC-NUMA systems to be built. This paper describes the motivation for building STiNG as well as its architecture and implementation. In addition, performance analysis is provided for On-Line Transaction Processing (OLTP) and Decision Support System (DSS) workloads. Finally, the status of the current implementation is reviewed.

5491773 Encoding system comprising a subband coder for subband coding of a wideband digital signal constituted by first and second signal components

REMIS is a key component of the Air Force Depot Maintenance System. It consists of 3.1 million lines of source code written in COBOL85, Tandem Application Language (TAL), and C. The system runs on a Tandem Symmetric Multiprocessor with nonstop SQL/MP DDL and a Tandem database. Northrop Grumman maintains REMIS at Wright-Patterson AFB for the Air Force Materiel System Group (MSG). The migration of REMIS was undertaken in support of the AF/A4M directive of the AFMC, ESC, 554 ELSW, 754 ELSG, and REMIS PMO 754 ELSG/LRX. The Northrop Grumman acted as prime contractor and integrator and developed a strategy to undertake the migration of REMIS in six increments into the GCSS-AF IF. Northrop Grumman undertook Increment-1 and Increment-2 in 2002, and Increment-3 in 2005–2006, respectively, with TSRI serving as a subcontractor providing automated information system transformation services. The purpose of the REMIS migration was both to demonstrate the feasibility and assess and realize benefits (economic, schedule, and qualitative) of using automated transformation to create a GCSS-AF resident version of the REMIS application. This project was a technically successful application of architecture-driven modernization (ADM) techniques to large-scale systems engineering, development, integration, and operational processes of a major component of the USAF IDMS. The focus of this case study is Increment-1 and Increment-3, which were technically successful demonstrations of ADM techniques applied to a large-scale systems engineering, development, integration, and operational processes for a major component of the USAF IDMS.

An overview of DB2 parallel edition

In this paper, we describe the architecture and features of DB2 Parallel Edition (PE). DB2 PE belongs to the IBM family of open DB2 client/server database products including DB2/6000, DB2/2, DB2 for HP-UX, and DB2 for the Solaris Operating Environment. DB2 PE employs a shared nothing architecture in which the database system consists of a set of independent logical database nodes. Each logical node represents a collection of system resources including, processes, main memory, disk storage, and communications, managed by an independent database manager. The logical nodes use message passing to exchange data with each other. Tables are partitioned across nodes using a hash partitioning strategy. The cost-based parallel query optimizer takes table partitioning information into account when generating parallel plans for execution by the runtime system. A DB2 PE system can be configured to contain one or more logical nodes per physical processor. For example, the system can be configured to implement one node per processor in a shared-nothing, MPP system or multiple nodes in a symmetric multiprocessor (SMP) system. This paper provides an overview of the storage model, query optimization, runtime system, utilities, and performance of DB2 Parallel Edition.

SP2 system architecture

Scalable parallel systems are increasingly being used today to address existing and emerging application areas that require performance levels significantly beyond what symmetric multiprocessors are capable of providing. These areas include traditional technical computing applications, commercial computing applications such as decision support and transaction processing, and emerging areas such as “grand challenge” applications, digital libraries, and video production and distribution. The IBM SP2™ is a general-purpose scalable parallel system designed to address a wide range of these applications. This paper gives an overview of the architecture and structure of SP2, discusses the rationale for the significant system design decisions that were made, indicates the extent to which key objectives were met, and identifies future system challenges and advanced technology development areas.

Some measurements of timeline gaps in VAX/VMS

The purpose of this article is to present measurements and some analysis of the distribution of interrupt-level timing glitches observed over a period of months in an instrumented dual-processor DEC VAX 6520 running VMS 5.4 with Symmetrical Multiprocessing. Each of the two CPUs is rated at 13 VUPs (VAX Unit of Processing), for a total of 26 VUPs. (A VUP is about half a MIP.) As the instrumented machine was in general use, no active experiments were attempted. These glitches translate into unavoidable gaps in the execution of user-level processes. The gaps are harmless unless the processes have deadlines

Design and analysis of master/slave multiprocessors

A simple model of master/slave processors is presented, along with two simple, practical scheduling algorithms. An approximate analysis of the model yields simple formulas for performance measures in terms of the hardware and workload parameters, and gives insight into the power and the limitations of master/slave systems. In particular, formulae are obtained for the maximal processing power (throughput) of the system, a quantity that remains bounded as the number of slave processors increases. This analysis is applicable to symmetric multiprocessors, where performance considerations such as cache performance may dictate asymmetric assignment of system tasks to the processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The upgraded Tevatron front end

We are replacing the computers which support the CAMAC crates in the Fermilab accelerator control system. We want a significant performance increase, but we still want to be able to service scores of different varieties of CAMAC cards in a manner essentially transparent to console applications software. Our new architecture is based on symmetric multiprocessing. Several processors on the same bus, each running identical software, work simultaneously at satisfying different pieces of a console's request for data. We dynamically adjust the load between the processors. We can obtain more processing power by simply plugging in more processors cards and rebooting. We describe in this paper what we believe to be the interesting architectural features of the new front-end computers. We also note how we use some of the advanced features of the Multibus™ II bus and the Intel 80386 processor design to achieve reliability and expandability of both hardware and software.

A queueing analysis of a symmetric multiprocessor with shared memories and buses

A queueing analysis of a symmetric multiprocessor with shared memories and buses