Symmetric Double-gate Junctionless Transistor Research Articles

A method for reduction of off state leakage current in symmetric DG JLT

A novel method for reduction of off state leakage current in a symmetric double gate junctionless transistor (DG JLT) is presented in this paper. In this technique a layer of dielectric has been placed at centre of the JLT. As major portion of leakage current flows through the centre, placing a dielectric at the centre will reduce the leakage current to large extent. An analytical model of drain current and threshold voltage for the proposed structure is developed. The model is validated by comparing it with simulation results obtained from TCAD (Technology Computer Aided Design). The model is in close agreement with TCAD results. The model as well as simulation results show that the JLT with dielectric layer placed at the centre has lower subthreshold current compared to the conventional JLT.

An Analytical Approach for Drain Current Modelling of a Symmetric Double Gate Junctionless Transistor

An Analytical Approach for Drain Current Modelling of a Symmetric Double Gate Junctionless Transistor

A Physics Based Approach for Threshold Voltage Modelling of Symmetric Double Gate Junctionless Transistor with Multi Material Gate

A Physics Based Approach for Threshold Voltage Modelling of Symmetric Double Gate Junctionless Transistor with Multi Material Gate

Empirical Model for Nonuniformly Doped Symmetric Double-Gate Junctionless Transistor

This paper demonstrates the influence of nonuniform doping on the electrostatics of symmetric double-gate junctionless transistor using empirical modeling scheme. To present the clear insight into the device electrostatics of nonuniform doped channel, the peak of the doping concentration has been varied from Si/SiO2 interface of front gate to the back gate. The parameters explored in this paper are surface potential, electric field, drain current, threshold voltage, subthreshold slope, and drain-induced barrier lowering for different straggle factors and channel lengths. By properly optimizing the straggle value and peak of the doping concentration, device performance can be tuned accordingly.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor (DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.

A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.

The effect of high-k gate dielectrics on device and circuit performances of a junctionless transistor

The impacts of high-k gate dielectric permittivity on the device and circuit performances of a double-gate junctionless transistor (DGJLT) are studied with the help of extensive device simulations. The results are compared with a conventional inversion mode double-gate metal oxide semiconductor field effect transistor (DG MOSFET) of same dimension. Drain induced barrier lowering, intrinsic gain $$(G_{m}R_{O})$$(GmRO), and unity gain cut-off frequency $$(f_{T})$$(fT) are degraded with an increase in gate dielectric permittivity $$(k)$$(k). The transconductance $$(G_{m})$$(Gm) and gate capacitance $$(C_{GG})$$(CGG) are slightly affected with increase in $$k$$k. The gain of CMOS single stage amplifier and delay of inverter are found to be decreasing and increasing, respectively, with increase in $$k$$k. In order to mitigate these short channel effects due to the high-k gate dielectrics, a hetero-gate-dielectric structure with symmetric double-gate junctionless transistor (HG-DGJLT) is studied. HG-DGJLT offers superior $$G_{m}, \, C_{GG}$$Gm,CGG and $$f_{T}$$fT compared to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT. However, intrinsic gain of HG-DGJLT is inferior to $$\hbox {SiO}_{2}$$SiO2-only and $$\hbox {HfO}_{2}$$HfO2-only DGJLT.

A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog Performance

In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.

Double-Gate Junctionless Transistor for Analog Applications

In this paper, analog performance of short channel symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The analog performance parameters, namely drain current (I(D)), transconductance (G(m)), transconductance/drain current ratio (G(m)/I(D)), early voltage (V(EA)), drain output conductance (G(D)), output resistance (R(o)), intrinsic gain (G(m)R(o)), gate to source capacitance (C(GS)), gate to drain capacitance (C(GD)) and unity gain cut-off frequency (f(T)) for the n-type DGJLT are systematically investigated with the help of extensive device simulations and are compared with conventional inversion mode symmetric double-gate transistor (DGMOS) of similar dimensions. DGJLT offers superior transconductance/drain current ratio and intrinsic gain in the subthreshold region than its inversion mode counterpart having same dimensions. However, DGMOS presents higher unity gain cut-off frequency which makes it suitable for high speed applications as compared to a DGJLT transistor.

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I D ), ON-state to OFF-state current ratio (I ON /I OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G m R O ), output conductance (G D ), transconductance/drain current ratio (G m /I D ) and unity gain cut-off frequency (f T ). The effects of varying the spacer dielectric constant (k sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.