Switching Noise Research Articles

A fully integrated temperature sensor with an inaccuracy of ±0.4 °C (3σ) from −55 to 150 °C

A high-accuracy fully integrated temperature sensor for a wide temperature range up to 150 °C is presented in this article. The sensing circuits with the asymmetric operational amplifier and bias current optimization is applied to eliminate the component mismatch error and enhance the accuracy. The asymmetric operational amplifier can remove the offset voltage avoiding the switching noise compared with the chopping method. An extended counting analog-to-digital convertor (ADC) is proposed as the readout interface due to its compact structure and high efficiency. An easily-achieved dynamic range improvement is devised. Benefited by the dynamic range improvement, the 14-bit ADC can achieve a resolution of 0.0156 °C. This temperature sensor is fabricated in a 0.18-μm CMOS process, and it achieves an accuracy of ±0.4 °C (3σ) from −55 to 150 °C.

A magnetic diagnostic suite for the Pegasus-III experiment.

Pegasus-III is an ultralow aspect ratio spherical tokamak providing a dedicated US experiment for comparative solenoid-free startup studies. A new magnetic diagnostic suite for equilibrium and low frequency (<200kHz) magnetohydrodynamic mode analysis has been installed. These new diagnostics address the significant challenges of measuring magnetic field in a high noise environment with the majority constrained to fit in an 8mm diagnostic gap on the high field side. Electrostatic switching noise generated by the 16 independent current feedback-controlled power supplies produces dVcm/dt ∼ 1kV/μs and volt level common mode noise on the magnetics. Immunity to this switching noise is accomplished through differential signal runs and signal processing, along with end-to-end electromagnetic interference shielding. The magnetic measurements are simultaneously digitized at 1MHz and conditioned by precision 8 pole Butterworth filters with a corner frequency of 200kHz to prevent aliasing down to the 16-bit level over the full passband. Ex-vessel calibrations of the Bp coils were completed with a typical uncertainty of <0.5%. Stray toroidal field pickup from coil misalignment or positioning errors is corrected using a physics-based model. Comparisons of the corrected measurements to modeling agree to within 1.3% on average. This is within the 1.5% measurement uncertainty that a sensitivity analysis determined is needed for accurate fast boundary and equilibrium reconstruction.

A novel etiology for automatic mode switching and ventricular noise reversion alerts: pulsed field ablation

A novel etiology for automatic mode switching and ventricular noise reversion alerts: pulsed field ablation

A Hybrid Beat Frequency Oscillation Suppression Strategy for DC Microgrids

In DC microgrids, parallel-connected power converters are commonly used to integrate distributed energy sources. However, interactions of power switching noises among these power converters could lead to large low-frequency beat frequency oscillations under certain conditions, which degrades system performance and reliability, especially for DC microgrids with parallel connected Boost converters. In this research, the output impedance model for multiple parallel-connected Boost converters is developed for beat frequency oscillation analysis, and then a hybrid method is proposed to address this issue. The proposed method includes separated switching frequency channels and additional line inductors. Experimental results validate the effectiveness of the proposed method.

Experimental electromagnetic compatibility of conducted electromagnetic interferences from an IGBT and a MOSFET in the power supply

Introduction. Most electromagnetic compatibility studies carried out in the context of power switch research are generally valid for low frequencies. This frequency restriction appears to be too restrictive for a complete analysis of the electromagnetic interference conducted. The novelty of this work lies in the load-dependent an optimal selection of IGBTs and MOSFETs for least-disturbance power switching in the frequency range from 150 kHz to 30 MHz, based on an optimal experimental selection procedure and show the impact of load value on switch switching and noise generation. Purpose. Analysis of the fundamental possibility of selecting a switching device with a power supply based on an experimental measurement which allows to increase the reliability of the entire mechanism operation and significantly simplify the design. Methods. In this paper, the proposed study is used and compared with experimental results at low and high frequencies. Then, a comparison is made for conducted electromagnetic interference (common-mode and differential-mode) generated by IGBT and MOSFET for different loads, and the proposed methodology is verified on an experiment suitable for predicting terminal overvoltage analysis and conducted electromagnetic interference problems. Practical value. The primary method for establishing a conducted electromagnetic interference source for switching devices is based on IGBT and a MOSFET depending on the resistive load. References 22, figures 17.

A Control Strategy for Achieving Constant Voltage Output with an Extensive ZVS Operating Range in Bidirectional Wireless EV Charging Systems

Variations in the coupling coefficient of loosely coupled transformers and dynamic loads have a significant impact on the overall performance of bidirectional inductive power transfer (BIPT) systems. However, a wide range of load and coupling coefficient variations are common in the actual charging process, which may cause the converter on both sides to operate in a hard switching state, resulting in switching noise, reduced efficiency, and potential safety concerns. In this paper, a triple-phase-shift control (TPSC) strategy is proposed to study the zero-voltage switching (ZVS) operating range and constant-voltage output (CVO) characteristics of the double-side-LCC (DS-LCC) topology. To ensure a CVO over the wide range of coupling coefficient variations, a dual-phase-shift control is introduced for AC voltage matching. Based on this, the third phase-shift angle control between the converters on both sides is introduced to ensure the ZVS realization. Meanwhile, the time-domain model is developed to analyze the rationality of the proposed third phase-shift angle and the ZVS operating range. Finally, the effectiveness of the proposed TPSC strategy is validated through a 1.5 kW experimental prototype with an air gap of 100–150 mm.

Enhanced Proportional Resonant – Second-Order General Integrators (EPR-SOGI) With Fuzzy Logic Control in Hybrid Renewable Energy Source-Based STATCOM

In this paper, the fuzzy-logic controllers (FLC)-based enhanced proportional resonant – second-order general integrators (SOGI) method for Static Compensator is provided to improve the quality of power. The Hybrid Renewable Energy Sources provide support for the quasi-Z- source inverters (qZSI) that is known as HRES-STATCOM. In the usual approach, the actual dc-link voltages of the inverters are controlled by the PI controllers using a fixed reference DC-link voltage, which may result in excessive switching loss and switching noise. As system or load characteristics vary in real-world applications, a low DC-link voltage may be required, resulting in less switching losses and noise. As a result, an FLC-based EPR-SOGI method has been suggested. This approach gives the optimal reference DC-link voltage, which reduces the switching losses and hence offers improved compensation in varying-parameter settings as well. In the framework of Matlab/Simulink, the EPR-SOGI algorithm is designed and then simulated for three distinct cases. According to the findings of the research, it is abundantly clear that the suggested algorithm is better than the conventional algorithm in terms of its adaptability and its robustness. A laboratory-developed experimental setup is also used to verify the superiority of the suggested algorithm over the traditional method.

DC Series Arc Fault Diagnosis Scheme Based on Hybrid Time and Frequency Features Using Artificial Learning Models

DC series arc faults pose a significant threat to the reliability of DC systems, particularly in DC generation units where aging components and high voltage levels contribute to their occurrence. Recognizing the severity of this issue, this study aimed to enhance DC arc fault detection by proposing an advanced recognition procedure. The methodology involves a sophisticated combination of current filtering using the Three-Sigma Rule in the time domain and the removal of switching noise in the frequency domain. To further enhance the diagnostic capabilities, the proposed method utilizes time and frequency signals generated from power supply-side signals as a reference input. The time–frequency features extracted from the filtered signals are then combined with artificial learning models. This fusion of advanced signal processing and machine learning techniques aims to capitalize on the strengths of both domains, providing a more comprehensive and effective means of detecting arc faults. The results of this detection process validate the effectiveness and consistency of the proposed DC arc failure identification schematic. This research contributes to the advancement of fault detection methodologies in DC systems, particularly by addressing the challenges associated with distinguishing arc-related distortions, ultimately enhancing the safety and dependability of DC electrical systems.

Novel EBG‐type power/ground network with open stub bridges for broadband SSN suppression

AbstractA novel electromagnetic bandgap power/ground (P/G) network is proposed by using λ/4 open stub resonators for the broadband suppression of the simultaneous switching noise. Since three λ/4 open stub resonators are linked to the bridge between the two cells as bandstop filter, the high‐order mode resonances can be effectively suppressed. The proposed P/G network is analyzed by the cavity modes, simulated by the full‐wave simulator, and validated by the measurement. A broadband simultaneous switching noise suppression from 0.6 to 7.6 GHz is achieved. Additionally, in comparison with the reference boards, the radiated emission has less electromagnetic interference, which validates the advantage of the proposed electromagnetic bandgap P/G network.

GaN Transistors’ Radiated Switching Noise Source Evidenced by Hall Sensor Experiments Toward Integration

GaN Transistors’ Radiated Switching Noise Source Evidenced by Hall Sensor Experiments Toward Integration

A high step-up multiphase interleaved boost converter for fuel cells power system

The fuel cells need the high step-up DC/DC converter with low current ripples to interface to the high voltage DC grid. A novel zero voltage switching high step-up multiphase interleaved boost converter (ZVS HSMIBC) is proposed in this paper. This new converter employs advantages of low input current ripples, high voltage step-up ratio, soft-switching operation, and low switching harmonics and noise. In this paper, the two-phase interleaved structure of the proposed ZVS HSMIBC is analyzed and researched in detail as a representative topology. The relevant conclusions also can apply to multiphase (3 and above) interleaved structure of the HSMIBC. Finally, an experimental prototype is built and test, the experimental results show that the proposed converter can operated under ZVS conditions with low input current ripples and low switching noise and harmonics. In addition, this converter can obtain high voltage step-up ratio up to 45 (mn = 8, d = 0.8) with high efficiency, and proportion of the experimental ratios to theoretical ratios is also high (not less than 0.8).

Comparative analysis of logic gates based on CMOS, FINFET, and CNFET: Characteristics and simulation insights

In the evolution of integrated circuit technology, chip size and performance enhancement stand as paramount and challenging domains of progress. Yet, a dearth of foundational simulations and comparisons for introductory purposes exists. Consequently, this study delves into an introduction of distinct advanced integrated circuit (IC) technologies: CMOS, FinFET, and CNTFET, dissecting their merits and limitations. Subsequently, a preliminary simulation is executed to authenticate specific characteristics inherent to these IC technologies. Discoveries indicate that as IC transistors scale down, there are marked improvements in transistor performance, encompassing aspects such as switching speed, noise immunity, power efficiency, and heat dissipation. Further, a simulation grounded on a NAND gate substantiates certain traits in CMOS and FinFET, specifically switching speed, propagation delay, and noise margin. The results illustrate a superior performance of FinFET over CMOS. Additionally, as CMOS technology scales, its efficacy enhances. Nonetheless, the present research and simulations hold potential uncertainties and constraints, paving avenues for more refined investigations in the future.

Performance analysis of PID controller and fuzzy logic controller for DC-DC boost converter.

Demand of Power electronics converter is increased due to the rapid increase of green re-sources. The distributed nature of uncontrolled renewable energy resources are connected with the grid via power electronics converter. DC-DC converters are high-frequency current conversion circuits that use transformers, inductors, and capacitors to smooth switching noise into regulated DC voltages. In this study, a comparative performance analysis of Proportional integral Derivative (PID) and fuzzy logic controller (FLC) for DC-DC Boost Converter is presented. PID-based controller for dynamic boosting of DC-DC boost converter was replaced by Fuzzy Inference system (FIS) to study the system behavior. Five different membership functions were performed to observe the response of the system for DC -DC boost converter with FIS controller. The performances of FIS-based controller and PID-based controller for DC-DC boost converter were compared in detail. Also, the proposed techniques for the switching mode of DC-DC converter have been applied. The performance analysis of both PID and fuzzy controller was simulated using MAT LAB. The results of FIS based approach are better than PID based controller in terms of transient responses.

Suppression of Simultaneous Switching Noise Using Embedded Capacitor Method in High-Speed Systems

Gbps signals are commonly used in modern high-speed IO designs. These systems require a high level of signal accuracy. However, these signals can cause current fluctuations at high frequencies due to parasitic inductance on the package and board, leading to significant changes in supply voltage. DDRX interfaces that transmit data up to 4.8 Gbps induce simultaneous switching noise (SSN) in the voltage regulator module (VRM). One of the adverse effects of SSN is timing jitter, also known as power supply-induced jitter. The amount of SSN is directly proportional to the number of signals on a parallel bus. Discrete capacitors may not be effective in reducing SSN impact when data is transmitted at high speeds. The current approach used to predict and evaluate errors in SSNs relies on the designer's expertise, which requires accurate estimates of packaging parasitic. In this paper, a practical approach to lessen SSN is presented through the use of embedded capacitors placed between planes and optimizing discrete capacitors by connecting them in a way that measures the impact of supply noise on the I/O transistor circuit performance at the DDRX interface. Two boards were designed, evaluated, and subsequently compared their results.

General fluctuation-dissipation relations embedded in Markov switching diffusion processes

We present an integral theory for the fluctuation-dissipation relations embedded in Markov switching diffusion processes, which mimic the fluctuations induced simultaneously by noise originating from different time-scale levels. The formulas for the extended Einstein’s relation in terms of second-order moments, as well as the auto and cross spectra are derived. Several universal properties for two types of fluctuations are proved: The thermally induced one remains globally constant for isothermal systems and its spectrum is Lorentzian; the fluctuation induced by the switching noise has distinctive scaling laws that are embedded in the auto and cross spectra.

Hybrid Solenoids Based on Magnetic Shape Memory Alloys

The mobility of today and tomorrow is characterized by technological change and new challenges in drive concepts such as electric or hydrogen vehicles. Abolishing conventional combustion engines creates even more need for switching or valve technology in mobility systems. For switching and controlling purposes, solenoids are used in large numbers and in a wide variety of applications, thus making a significant contribution to the overall success of the energy transition, and not only in the automotive sector. Despite their long existence, continued research is being carried out on solenoids involving new materials and actuator concepts. Great interest is focused on providing an adjustable force–displacement characteristic while simultaneously reducing the noise during switching. At IKFF, research is being conducted on hybrid electromagnets in the border area of switching and holding solenoids. This paper aims to present the major advantages of this hybrid drive concept based on an electromagnetic FEA simulation study of two drive concepts and specially developed and characterized prototypes with magnetic shape memory (MSM) alloys. The concepts differ in the spatial orientation of the MSM sticks to generate an active stroke of the plunger, which contributes to a beneficial force–displacement characteristic and lower power consumption while minimizing switching noise.

A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS

This paper presents a 4-wire, 3-level, and 16-Gb/s/wire transceiver array for short-reach interconnects. The proposed transceiver adopts the balanced single-ended signaling (BASES) to reduce the simultaneous switching noise (SSN) and the electro-magnetic interference (EMI). The four transmit encoders and voltage-mode drivers produce three-level, common-mode-balanced, and multi-lane signals. The receive terminations and equalizers utilize the CM-balancing property of the BASES coding to recover the transmitted signals with a high noise rejection capability. The 4-wire transceiver was fabricated in a 28-nm CMOS technology and achieved a 64-Gb/s aggregate data rate with 3.15-pJ/bit energy efficiency.

Optimal LCL-filter design for a single-phase grid-connected inverter using metaheuristic algorithms

The inductor-capacitor-inductor (LCL) filter is used to lower the high-frequency switching noise of a grid-connected inverter (GCI). However, a robust design of the LCL filter is a challenge due to its complex model, variations in the operating conditions of the grid, and its stability gain margin. Therefore, this paper designs an optimal LCL filter for GCI and considers the changing grid conditions. This paper utilized four metaheuristic optimization algorithms, including the Whale Optimization Algorithm, the Circle Search Algorithm, the Particle Swarm Optimization, and the gray Wolf Optimization. These algorithms are applied to minimize the total harmonic distortion (THD) and the error between the reference and real grid current. The robustness of the optimal LCL filter is investigated under transient and steady states of the grid by using MATLAB/SIMULINK and real-time simulations. The obtained results revealed that the optimal LCL filter is capable of reducing the THD under different grid variations.

A Comprehensive Noise Model for Wideband and High Frame Rate Electrical Impedance Tomography Systems

Clinical applications call for comprehensive performances of electrical impedance tomography (EIT) system, including sufficient signal-to-noise ratio (SNR), high frame-per-second (Fps), and wide bandwidth. In this article, thorough analyses of switching noise in an EIT system are presented. The energy of switching noise is split into two parts: spurs and extra quantization noise of analog-to-digital converter (ADC). Based on the characteristics of switching noise, a comprehensive noise model of EIT systems with digital matched filter, is proposed. The impacts of switching noise, frame rate, and bandwidth of an EIT system are considered in the noise model. Simulation and experiment conducted in a laboratory-built EIT system are employed to validate the noise model. Test results show that the EIT system can obtain an average SNR greater than 94dB with a frame rate of 31Fps and a bandwidth of 2MHz, and an average SNR greater than 90dB with a frame rate of 31 Fps and a bandwidth of 10MHz, under the guidance of the proposed model. Overall, this work provides a novel and comprehensive noise model by including the impacts of switching noise, frame rate, and bandwidth, which can serve as a guide to improve the comprehensive performance of an EIT system for clinical applications.

Performance comparison of vertically stacked nanosheet CFET and standard CMOS without and with parasitic channels

The threshold voltage regulation and the effect of parasitic channels are important issues in CFET. In this paper, the characteristics of the complementary field-effect transistor (CFET) were simulated based on a self-aligned vertically stacked nanosheet fabrication process at the 2 nm technology node by TCAD simulation. The electrical characteristics of CFET were matched by adjusting the metal work function. We analyzed the static characteristics and transient response, as well as the impact of the parasitic channel. Compared to standard CMOS with the same process, the switching threshold and noise margin of CFET are approximately equal to CMOS, but the power and speed are slightly better than CMOS because nFET and pFET of CFET share the same gate to have small parasitic capacitance. With the height of the parasitic channel increasing, the off-state current and parasitic capacitance of the device increase, but CFET suppresses the bad effect of the parasitic channel and changes less. CFET with the stacked nanosheet structure has greater advantages than CMOS, can tolerate the parasitic channel from the fabrication process, and improve performance in the perspective of front-end-of-line (FEOL).