Switching Noise Research Articles

A Mixed-Signal Adaptive Ripple Canceler for Switching Regulators Providing 18 dB-24 dB of Ripple Rejection up to 1 MHz

A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components.

Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation

For the purpose of evaluating the impact of excitation on double data rate (DDR) interface system transmission performance, a methodology for generating the worst-case excitation is proposed for signal integrity (SI) and power integrity (PI) co-simulation. The excitation is produced with the pseudo random bit sequence (PRBS) gated by a square wave of the resonant frequency of the system power distribution network (PDN). The PRBS can reflect non-ideal factors as crosstalk, reflection and loss in the signal line, and the resonant frequency of the PDN can guarantee the maximum simultaneous switching noise (SSN). A data transmission performance simulation environment of currently widely used low power double data rate SDRAM4 (LPDDR4) is constructed based on the advanced I/O buffer information specification Plus (IBIS Plus) model. Compared with the ordinary PRBS excitation, in terms of eye diagrams, the proposed worst-case excitation reduces the eye width and eye height by 4.7% and 19.9%, respectively. Further analysis also proved that 1/2 duty ratio of the gating wave can maximize the influence from the power noise. In conclusion, the proposed worst-case excitation and test environment provide an improved SI/PI co-simulation scenario for the examination of the robustness of DDR system data transmission performance.

A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC–DC Switching Converters

The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μ A and reduces the switching power loss through variable switching frequency control. With a load step of 1–20 mA, the transient response time is 1.3 μ s and the peak current efficiency is 99.8% at heavy loads.

Delta-Sigma Modulator-Based Step-Up DC–DC Converter with Dynamic Output Voltage Scaling

The switching noise and conversion efficiency of step-up DC-DC converters need to be improved to meet increasing demand. The delta-sigma modulation (DSM) technique is typically used to improve the performance of buck converters; however, this control scheme is not directly applicable for boost converters. This paper presents a boost DC–DC converter using a continuous-time delta-sigma modulator (DSM) controller for battery-powered and noise-sensitive applications. The proposed converter can adjust a wide range of output voltages dynamically by clamping the maximum duty cycle of the DSM, thus enabling stable and robust transient responses of the converter. The switching harmonics in the converter output are reduced effectively by the noise shaping property of the modulator. Moreover, the converter does not suffer from instability of mode switching due to the use of a fixed third-order DSM. Fabricated in a 180 nm CMOS, the converter occupies an active area of 0.76 mm2. It produced an output voltage ranging from 2.5 V to 5.0 V at an input voltage of 2.0 V and achieved a peak conversion efficiency of 95.5%. The output voltage ripples were maintained under 25 mV for all load conditions. A low noise output spectrum with a first spurious peak located −91 dBc from the signal was achieved.

A stochastic switched SIRS epidemic model with nonlinear incidence and vaccination: Stationary distribution and extinction

In this paper, a stochastic epidemic system with both switching noise and white noise is proposed to research the dynamics of the diseases. Nonlinear incidence and vaccination strategies are also considered in the proposed model. By using the method of stochastic analysis, we point out the key parameters that determine the persistence and extinction of the diseases. Specifically, if [Formula: see text] is greater than 0, the stochastic system has a unique ergodic stationary distribution; while if [Formula: see text] is less than 0, the diseases will be extinct at an exponential rate.

Synchronization of complex networks with Markovian switching coupling via aperiodically quantized intermittent pinning control

AbstractIn this paper, we investigate the synchronization of complex networks with Markovian switching couplings. The complex network we deal with subjects to Markovian switching couplings, noise perturbations and internal and outer time‐varying delays, which is a more general model and has wide applications. The control scheme we employ is the aperiodically quantized intermittent pinning control. By using the Lyapunov‐Krasovskii functional, It 's formula and the linear matrix inequality (LMI), sufficient conditions for synchronization of complex networks with Markovian switching couplings are obtained. A numerical simulation is provided to demonstrate the validity of our theoretical results.

A sub-harmonic injection locking clock multiplier with FLL PVT calibrator

Using the sub-harmonic injection locking technique, an enhanced differential Digitally Controlled Ring Oscillator (DCRO) with improved phase noise performance is proposed in this paper. All circuit blocks were implemented using digital design flow and designed using a hardware description language. A Frequency Locked Loop-based Process, Voltage and Temperature (PVT) calibrator was utilized to overcome PVT variations. The design was fabricated in 65 nm CMOS technology and its area is 0.017 mm2. The measured phase noise at 1 MHz offset and RMS jitter are −128 dB/Hz and 197fs, respectively. The design was tested in the presence of voltage and temperature variations. The maximum jitter difference percentage is 13.7% at 70 °C and 1.1 V and the phase noise value changes by a maximum of 0.7 dB over the whole range of voltages and temperatures. Furthermore, when the design was tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the DCRO.

MTL-based modeling and analysis of the effects of TSV noise coupling on the power delivery network in 3D ICs

With the application of heterogeneous integration and advanced packaging technologies, the use of through-silicon vias (TSVs) to deliver the power supply has become popular in the design of stacked chips in three-dimensional integrated circuits. High-density vertical interconnections offer higher speed and bandwidth, but the electromagnetic coupling effect among TSVs becomes more serious. Therefore, investigation of the noise coupling among TSVs and analysis of its impact on the power supply become important considerations. An analytical model based on the theory of multiconductor transmission lines (MTLs) is presented herein to discuss such TSV noise coupling. The method can accurately and quickly estimate the noise coupling coefficient among a large number of TSVs and offers good practicability for similar structures and even the TSVs of complex structures. Further, the influence of TSV noise coupling and simultaneous switching noise from switching circuits on the supplied power voltage is discussed. Finally, the parameters of an actual Intel chip are taken as an example to analyze the supplied power voltage that reaches complementary metal–oxide–semiconductor (CMOS) circuits through the three-dimensional (3D) power distribution network after considering the power supply noise. The presented model is validated by comparing the calculation results with those obtained from a full-wave simulator. The runtime and memory consumption requirements are lower than those of the full-wave simulator.

Adaptive DC-Link Voltage Control for Shunt Active Power Filters Based on Model Predictive Control

DC-link voltage directly affects the compensation range and performance of shunt active power filters (SAPFs). DC-link voltage in SAPF is generally high, fixed, and dependent on rated power. DC-link voltage could become excessive in low-load conditions, which increases switching loss and switching noise. Optimized DC-link voltage was obtained in this study to enhance compensation adaptability for variable nonlinear loads and fluctuation in grid voltage. We proposed a novel adaptive DC-link voltage control for SAPFs, which reduced switching noise and switching loss during operation. The proposed DC-link voltage control method employed model predictive current control, proportional voltage control and calculation of optimal DC-link voltage. A real-time observer, which was insensitive to distorted grid condition, was used to capture peak grid voltage. Finally, simulations and the results of experiments were used to verify the effectiveness and feasibility of the proposed DC-link voltage control method.

DC Series Arc Fault Detection Algorithm for Distributed Energy Resources Using Arc Fault Impedance Modeling

Arc fault detection is important technology to guarantee the safety of power systems and is therefore essential for producing practical power systems for real-world applications. However, fuses and arc fault detection devices (AFDD) struggle to detect series arc faults in DC systems, because the series arc fault induces small current variation between the normal and abnormal conditions. In addition, switching noise from the grid-connected inverter makes detecting arc fault conditions even more difficult. This paper proposes arc fault detection algorithm based on the relative comparison of current variability in terms of frequency spectrum and time series. The operational principle of the proposed algorithm is analyzed to detect the arc fault condition. In addition, the investigation of arc fault impedance using the small-signal modeling can obtain the resonant frequency of arc fault condition at low frequency range. From the impedance model, the frequency analysis range can be designed to avoid the switching noise of inverter. The performance of proposed arc fault detection algorithm is verified with a 3.8 kW grid-connected PV system and arc fault generator.

An Improved Genetic Algorithm for Optimizing EBG Structure With Ultra-Wideband SSN Suppression Performance of Mixed Signal Systems

In this paper, an improved genetic algorithm (GA) for automatically optimizing electromagnetic bandgap (EBG) structure with good power integrity performance is presented. The traditional GA is improved in several ways including Hamming Distance initialization, elite selection and non-repeating crossover, which can generate initial population charactering solution space in detail, increase crossover efficiency, and accelerate convergence. Furthermore, an EBG structure for power distribution network is optimized with the presented GA method to improve the performances of power integrity. The simultaneous switching noise propagation can be prohibited from 0.38 GHz to 20 GHz with a suppression level of -60 dB. Good agreements between the measured results and the simulation ones are observed.

Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs

In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias ( $\mu $ TSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than $4\times $ in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (P&R)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25%–30% improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level P&R of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal–insulator–metal cap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backside-PDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.

Analysis and Improvement of Capacitance Effects in 360–800 Hz Variable On-Time Controlled CRM Boost PFC Converters

In critical conduction mode (CRM) boost power factor correction (PFC) converters, the input filter capacitor (IFC) is used to limit the propagation of switching noise into the ac line and the inherently existing parasitic capacitance of power semiconductor devices resonates with the boost inductor to achieve soft switching, which is voltage dependent and nonlinear. However, IFC leads to the crossover distortion of the rectified input voltage and thus the zero-crossing distortion of input current, which is ignored at the utility line frequency (50-60 Hz) since the effect of IFC is relatively small in this case. However, for wide variable frequency (360-800 Hz) power system, the effect of IFC becomes severe and unnegligible, which causes the deterioration of input current total harmonics distortion (THD). Besides, the nonlinearity of the parasitic capacitance is ignored and an equivalent constant linear capacitance is used in existing variable on-time (VOT) controls, which will cause the inaccuracy of VOT control, and thus, exacerbates the input current distortion. In order to improve the input current THD at high line frequency, this article proposes the IFC compensation method to minimize the effect of IFC and a variable parameter control is also achieved to suppress the effect of nonlinear parasitic capacitance. The experimental results of an 115-Vac-input 160-W/270-Vdc-output CRM boost PFC prototype are presented to verify the effectiveness and advantages of the proposed VOT methods. With the proposed methods, the input current THD is only 2.04% at 360 Hz input with full load and 3.14% at 800 Hz input with full load.

A Novel Automatically Designed EBG Structure by Improved GA for Ultrawideband SSN Mitigation of System in Package

In this article, a novel automatically designed electromagnetic bandgap (EBG) structure is presented to prohibit the simultaneous switching noise (SSN) propagation of a system in package. The tool employed for the automatic EBG design is the improved genetic algorithm (GA), which has the advantages of rapid convergence and high precision by combining several improvements reasonably. Meanwhile, the equivalent circuit model and the dispersion diagram of the proposed structure are established to interpret the electromagnetic characteristics of the designed power distribution network (PDN). By removing some patches in a specific area determined by the GA, the surface impedance of PDN can be increased to reduce the SSN coupling. The SSN transmission can be suppressed from 0.37 to 20 GHz at a mitigation level of -50 dB. The measured results agree well with the simulated ones.

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO

This article demonstrates enhanced power (P) and electromagnetic (EM) side-channel analysis (SCA) attack resistance of standard (unprotected) 128-bit advanced encryption standard (AES) engines with parallel (P-AES, 128-bit) and serial (S-AES, 8-bit) datapaths and a 128-bit SIMON engine with the bit-serial (1-bit) datapath by an on-die security-aware all-digital low-dropout (DLDO) regulator. The proposed DLDO improves SCA resistance using control-loop-induced perturbations in a nominal DLDO, enhanced by a random switching noise injector (SNI) by power-stage control and a randomized reference voltage (R-VREF) generator coupled with all-digital clock modulation (ADCM). SCA performed on the measured power/EM signatures acquired from a 130-nm CMOS testchip demonstrates up to 25 $\times $ reduction in test vector leakage assessment (TVLA) leakage for P-AES and 3579 $\times $ , 2182 $\times $ , and 500 $\times $ increase in minimum-traces-to-disclose (MTD) 80% of the subkeys for P-AES, S-AES, and SIMON cores, respectively, with respect to correlation power analysis (CPA) and correlation EM analysis (CEMA).

Electrical studies of Barkhausen switching noise in ferroelectric lead zirconate titanate (PZT) and BaTiO3: critical exponents and temperature-dependence

Previous studies of Barkhausen noise in PZT have been limited to the energy spectrum (slew rate response voltages versus time), showing agreement with avalanche models; in barium titanate other exponents have been measured acoustically, but only at ambient temperatures. In the present study we report the Omori exponent (0.95 0.03) for aftershocks in PZT and extend the barium titanate studies to a wider range of temperature.

A Differential Push-Pull Voltage Mode VCSEL Driver in 65-nm CMOS

Improving power-conversion efficiency (PCE) of VCSEL drivers is paramount to improve the overall energy efficiency of the entire optical link for high-performance computing and datacenters. VCSEL diodes are normally driven single-ended with pseudo-differential current-mode drivers to maintain signal integrity. However, such conventional drivers consume significant power and are often unable to compensate for supply switching noise due to package parasitics at high data-rates. We propose a differential push-pull voltage-mode VCSEL driver to mitigate bondwire parasitics, reduce power consumption, and leverage CMOS process scaling to its maximum advantage. A proof-of-concept prototype in 65-nm CMOS process achieves the highest ever-reported PCE of 18.7 % for VCSEL drivers when normalized to VCSEL slope efficiency. It uses an asymmetric 3-tap rise and fall-based pre-emphasis to achieve a total energy/bit of 1.52 pJ/b at 16 Gb/s with an average optical power output of 1.34 dBm, OMA of 2.1 dBm, and extinction ratio of 5.92 dB.

Novel electromagnetic bandgap structure for wideband suppression of simultaneous switching noise

A novel electromagnetic bandgap (EBG) structure is proposed to suppress the simultaneous switching noise in high-speed circuits. The proposed EBG pattern is etched on the power plane while the ground plane remains intact. The unit is composed of an S-bridge EBG embedded with a coplanar EBG. The proposed EBG structure possesses an ultrawide bandgap extending from 0.28 to 25 GHz when the suppression depth is -45 dB. A prototype of the proposed EBG power plane is fabricated and tested, and good agreement is achieved between the simulation and the measurement.

Interview

Wen-Sheng Zhao from Hangzhou University, China, talks to Electronics Letters about the paper ‘Novel electromagnetic bandgap structure for wideband suppression of simultaneous switching noise’, page 1243 Wen-Sheng Zhao My research fields include interconnect modelling, multiphysics simulations and microwave sensor design. My major research topic is signal and power analysis of silicon via (TSV)-based 3D integrated systems. In recent years, the fourth industry revolution has shown an urgent need to develop next generation memory modules. As a key technology of industry 4.0, TSV-based high-bandwidth memory (HBM) has attracted a lot of interest from both the research and industrial worlds. To guarantee the system performance, it is necessary to perform signal/power/thermal integrity analysis for an HBM module. We are currently working on the issues related to the physical design of HBM modules (such as TSV modeling, equaliser design, and power noise suppression). Modern circuits are developing towards miniaturisation, high frequency and low power consumption, which puts strict constraints on the signal and power integrity design. For example, the operating voltages are continuously lowered, thereby limiting noise margin in power distribution network (PDN). Under such circumstances, power/ground noise is becoming a serious problem. To resolve this issue, various techniques including decoupling capacitor and electromagnetic bandgap (EBG) have been proposed and are under study. In comparison with decoupling capacitor, EBG structure can provide wideband noise suppression, and has been widely explored in the chip, package, and board. To improve the system performance, it is always desirable to increase the stopband bandwidth and rejection level of EBG structure. In this Letter, a power plane with coplanar EBG etched in the S-bridge EBG was proposed. With the proposed EBG structure, an ultrawide bandgap from 0.28 to 25 GHz with a high suppression level of -45 dB was achieved. Moreover, the signal integrity performance of the proposed EBG power plane was examined. The signal integrity can be ensured by utilising differential traces as the transmission structure. The proposed design can be used to reduce power/ground noise efficiently for mixed signal systems. We expect the proposed design to provide performance improvements in various mixed-signal systems in the immediate future. Currently, we are also working on developing EBG structures for silicon interposer and on-chip PDN. In the longer term, we expect that the EBG structures can be further explored and used in the physical design optimisation of HBM systems. As the clock frequency of the circuit system is continuously increased, the frequency of the simultaneous switching noise (SSN) also increases. However, the low-frequency components of the noise are not reduced accordingly. Therefore, the major issue we faced was developing a wide stopband EBG structure with a low cutoff frequency. Moreover, as grooves etched on the power/ground plane have an adverse impact on the signal transmission, we had to pay special attention to ensure signal integrity in the EBG design procedure. When we began studying TSV technologies, there was very little real-world deployment. Although several semiconductor giants such as Samsung presented some TSV based memory modules, these systems remained in the laboratory stage. Nowadays, TSV technology has matured, and the TSV-based HBM modules have been used in many graphics processing units since 2015. We are currently working on the physical design and optimisation (including signal and power integrity analysis) for TSV-based integrated systems. We have seen the introduction of many kinds of techniques (e.g., EBG, equaliser, differential signaling, and active decoupling) which will be helpful for future designs. There is no doubt that further improvements are always desirable to promote wide applications of TSV based integrated systems.

Suppression of Wideband Simultaneous Switching Noise Through Application of a Partial Electromagnetic Band-Gap Structure in Multilayer Printed Circuit Boards

Adding mushroom-like electromagnetic band-gap (EBG) structures to split power planes can produce wideband suppression of ground bounce noise in high-speed printed circuit boards. Practical equations are used to estimate the stop-band performance of EBG structures within parallel power planes. In this article, a mushroom-like EBG and power-bus structure are derived using the modified nodal analysis (MNA) method. Equations calculated using the MNA method are easily programmable. The partial EBG structures developed in this article can suppress noise from electromagnetic (EM) interference within parallel plates in the power bus. Several examples below show that similar results can be obtained in measurements, in EM simulations software, and in derived equations. The proposed structure enhanced the suppression of simultaneous switching noise coupling (≤-40 dB) within the range of 260 MHz to 10 GHz.