Switching Block Research Articles

A Scalable Hierarchical Dynamic PV Array Reconfiguration under Partial Shading

Photovoltaic (PV) arrays are often affected by partial shading (PS), which can significantly reduce their power output. Dynamic reconfiguration is a promising technique for mitigating the negative effects of PS by adjusting the electrical connections of the PV modules in real-time. This paper introduces a hierarchical-based switching block scheme for the dynamic reconfiguration of PV arrays under PS conditions. With the aim of mitigating the negative impact of PS on PV arrays, the proposed system employs a low complexity and easily scalable architecture, making it well-suited for practical applications. Comparative assessments against conventional configurations such as bridge-linked (BL), total-cross-tied (TCT), and series–parallel (SP) reveal superior energy harvesting efficiency for the proposed system under various shading conditions. The hierarchical switching block architecture, featuring multiple levels of switching blocks, enables efficient and flexible reconfiguration of the PV array, even in the presence of complex shading patterns. Through extensive simulations, the system consistently outperforms conventional configurations by adapting effectively to changing shading patterns and optimizing the PV array’s output. The proposed switching block (SB) reconfiguration technique significantly outperforms existing methods like TCT, Sudoku, dynamic proposals, and Magic Square in terms of both power generation (up to 42.52% increase) and efficiency (up to 42.13% improvement) under diverse partial shading conditions. The proposed hierarchical-based switching block scheme thus presents a promising solution for enhancing the dynamic reconfiguration of PV arrays under PS conditions, offering a balance between low complexity, scalability, and superior energy harvesting efficiency for practical applications in the realm of solar energy.

Social isolation during the COVID-19 pandemic is associated with the decline in cognitive functioning in young adults

Coronaviruses have caused widespread disease and death worldwide, leading to the implementation of lockdown measures and the closure of educational institutions in various countries. This research aims to investigate the impact of social isolation on the cognitive functioning of young students. The study included 84 subjects, with 48 being socially isolated and 36 non-isolated individuals. The participants’ mental health was assessed using the Mini-Mental State Examination (MMSE), while cognitive functions were evaluated through attention-switching tasks (AST), pattern recognition memory (PRM), and choice reaction time (CRT) tests utilizing the Cambridge Neuropsychological Automated Battery (CANTAB) software. The socially isolated group had an average age of 21.3 ± 1.1 years, whereas the non-isolated group had an average age of 22.8 ± 2.0 years. The MMSE scores were 25.8 ± 1.6 for the socially isolated group and 28.6 ± 1.3 for the non-isolated group. In terms of cognitive functioning, there were significant differences (p = 0.000) observed in the values of AST correct latency for non-switching blocks (blocks 3 and 5) between the socially isolated group (608.1 ± 139.2) and the non-isolated group (499.5 ± 67.8). Similarly, the AST mean correct latency for switching blocks (block 7) was significantly different (p = 0.012) between the socially isolated group (784.4 ± 212.5) and the non-isolated group (671.8 ± 175.6). The socially isolated group exhibited significantly higher values in AST correct mean latency, AST congruent mean latency, AST incongruent mean latency, and AST percent mean correct trials compared to the non-isolated group. Additionally, the PRM mean percent correct significantly differed (p = 0.000) between the isolated group (81.3 ± 12.0) and the non-isolated group (91.9 ± 9.2). The isolated group also showed a higher CRT correct mean latency (482.4 ± 128.9) than the non-isolated group (451.0 ± 59.0), however the difference was not significant. In conclusion, social isolation during the COVID-19 pandemic has resulted in a decline in the cognitive functioning of young students.

Saccadic latency differences in preclinical Alzheimer’s disease

AbstractBackgroundPrevious studies indicate that individuals with mild cognitive impairment (MCI) or Alzheimer’s disease (AD) have higher latencies on anti‐saccade tasks than healthy controls. We investigated whether this difference in latency appears even earlier, in cognitively healthy (CH) individuals at high risk of cognitive decline to MCI or AD and whether subliminal priming or task switching further impacted this latency difference.MethodWe studied CH participants whose cerebrospinal fluid (CSF) amyloid / tau ratio was normal (≥2.7132, low risk) or pathological (<2.7132, high risk) (PMID: 24260210). The testing paradigm included three blocks: (1) all saccades, (2) all anti‐saccades, and (3) patterned task switching with two saccades followed by two anti‐saccades. Trials began with a green (saccade) or red (anti‐saccade) cue appearing at a central fixation point. Then, a masked subliminal cue appeared on the right or left, followed by a target congruent or incongruent with the subliminal prime location. Trials ended 1000 ms after the participant first looked directly at the target for saccade trials or away from the target for anti‐saccade trials.ResultPreliminary results (n = 19, 3 high risk) using a 3‐way mixed ANOVA (d.f. = 3484) indicate that high risk participants perform slower across all conditions (F = 26.36, p <<< 0.001). This effect is especially pronounced when task switching (F = 3.41, p < 0.05), with high risk participants performing 70.9 ms slower in the task switching block (Bonferroni‐corrected p = 6.62×10−6, 95% CI = [29.8, 112]). During the block with all anti‐saccades, however, the difference in performance is not significant (Bonferroni‐corrected p = 0.78), unlike the effects previously observed in individuals with MCI or AD. Additionally, subliminal cues do not show a significant overall effect on behavioral data (F = 2.32, p = 0.13).ConclusionPilot results indicate that latency differences when task switching between saccade and anti‐saccade tasks exist in CH people at high risk of cognitive decline. Because eye tracking tasks are much less invasive and expensive than spinal taps, they could provide a potential screening tool for those at risk of cognitive decline.

Tracking Occupant Activities in Autonomous Vehicles Using Capacitive Sensing

Autonomous vehicles (AV) are a promising contemporary engineering innovation. Since they have no human drivers, their vehicle controllers must be fully informed of the activities of their occupants in vehicle seats so that occupant safety and comfort can be guaranteed. This paper introduces a system that employs capacitive sensing and machine learning to inform the controller of occupant activities, like actions and posture changes. The system facilitates capacitive sensing by deploying a capacitance-sensing mat on the vehicle seat. A sensing circuitry connected to the mat measures all its capacitances continuously. Since an occupant’s body induces variations in these capacitances, temporal sequences of capacitance measurements represent various occupant activities in the vehicle seat. Subsequently, the system converts capacitance measurements corresponding to every time step to two grayscale capacitance-sensing images (CSIs). The CSIs, in turn, yield a feature vector corresponding to every time step, thereby building a dataset of temporal sequences of features. The system’s machine-learning unit tracks and recognizes occupant actions and posture changes using an action-recognition block, which is essentially a long short-term memory (LSTM) network trained on a dataset of temporal sequences of either features or capacitance measurements corresponding to various occupant actions. If the occupant remains stationary, a switching block in the unit disables the action-recognition block and enables a posture-recognition block. The latter is a k -nearest-neighbor ( k NN) classifier trained on a dataset of features to recognize stationary occupant postures. This paper validates the system’s performance and investigates its deployment for real-time tracking of occupant activities in AVs.

Gate Driver Circuits With Discrete Components for GaN-Based Multilevel Multi-Inductor Hybrid Converter

Gate driver circuits to ensure proper turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> for power switches are essential parts of a power converter design. They become significantly challenging for multilevel converters, where multiple switches are operated at active voltage domains. The recent favorable use of gallium nitride devices for power switches makes gate driving even more difficult as the switch performance and reliability are very sensitive to the variations of the gate driving signals and power rails compared with traditional power MOSFETs. This article discusses gate driving methods using a multilevel multi-inductor hybrid (MIH) converter as the demonstration prototype to address two key challenges in designing gate drivers: 1) providing level-shifted pulsewidth modulation signals to active voltage domains and 2) powering schemes for gate driver circuits. To solve the first challenge, an optimal use of available half-bridge drivers is proposed to eliminate the need for separate signal isolator chips. This method was implemented and verified in an MIH converter prototype for 48-V point-of-load applications using three different powering schemes for gate drivers, including isolated power modules, regulated supplies from switch blocking voltages, and cascaded bootstrap power rails with regulations. The gate driver techniques and powering schemes are compared experimentally in terms of performance to illustrate their benefits and tradeoffs.

A novel high‐voltage solid‐state switch based on the SiC MOSFET series and its overcurrent protection

AbstractAll‐solid‐state switches are one of the core components of pulsed power supply systems. However, the voltage level of a single switch is limited. By optimizing the chip structure, the voltage level of a single switch can be improved. Due to the immaturity of the production process and the positive correlation between the blocking voltage and the on‐resistance of the switch, it is difficult to improve the blocking voltage and the continuous forward current of a single switch simultaneously. The series‐connected switch is a way to increase the switch's blocking voltage without reducing the switch's continuous forward current. Magnetically coupled isolated drive and resistor‐capacitor forced voltage equalization techniques are investigated to increase the blocking voltage of the switches using multiple SiC metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) in series connections. Meanwhile, a special overcurrent protection scheme is designed to improve the reliability of the series‐connected switch. Finally, a high‐voltage solid‐state switch is developed based on the SiC MOSFET series connections, whose output pulse width is adjustable from 20 to 300 μs, frequency is adjustable from 1 Hz to 3 kHz, the maximum output voltage can reach 57 kV (1 Hz), and the overcurrent protection time is about 1 μs.

Cascaded Multilevel Rectifiers for Open-End Winding PMSM

This article proposes three-phase cascaded multilevel rectifiers for wind energy conversion system applications. These configurations operate as machine-side converters and play an essential role in the integration of wind power generation units. The proposed rectifiers are connected to a permanent magnet synchronous machine by an open-end winding arrangement, making the ac–dc conversion of the power delivered with high-power factor operation. Their structures are composed of a combination of a converter based on Vienna rectifiers and one H-bridge per phase with a floating capacitor. Compared with the conventional configurations, the proposed ones provide sinusoidal currents with lower harmonic distortion using, proportionally, a fewer number of controlled switches. Furthermore, they can operate with a lower switch blocking voltage. These features make them attractive options for industrial applications due to their good performance, providing an interesting cost–benefit. The system model, pulsewidth modulation technique, capacitor voltage balancing, and control strategy are detailed. Computer simulations and experimental tests are provided in order to validate their feasibility.

A Scalable Low-Power Optical Chip: Realization and Static Loss Analysis

Optical interconnects outperforms the traditional electrical interconnects with lower power consumption, higher bandwidth density and scalability. We propose a scalable optical interconnect for on- chip core-to-memory communication. The key part of the optical interconnect is scalable optical switching blocks, which use less microring resonators with different wavelengths to provide higher parallelism for the memory access communication. We demonstrate the 4-port switching block with six microring resonators. The experimental results show the average insertion loss of 4-port optical switching block is 6.956 dB.

A Fully Integrated Power Converter for Thermoelectric Energy Harvesting With 81% Peak Efficiency and 6.4-mV Minimum Input Voltage

This letter introduces a fully integrated inductive power converter for thermal energy harvesting using the thermoelectric generator (TEG). With a three-step self-start block, the power converter can cold-start from 83&#x00A0;mV. After self-start, the minimum input voltage to sustain the power converter operation is only 6.4&#x00A0;mV. An integrated maximum power point tracking block keeps impedance matching at the TEG output. A novel low-power zero-current switching block realizes accurate switching with little overhead. The proposed power converter is implemented in a 55-nm CMOS process and achieves&#x00A0;81&#x0025; peak end-to-end efficiency.

Vienna Rectifiers for WECS Applications With Open-End Winding PMSM

This article proposes three-phase configurations for wind energy conversion system applications. The proposed topologies are based on Vienna rectifiers and they have a reduced number of controlled switches, which may allow reducing size and costs. Despite they can work with other arrangements, the proposed structures operate at an open-end winding configuration in this article, providing some benefits over the traditional ones. Compared to the conventional topology, the proposed ones provide a better power quality employing, proportionally, a fewer number of controlled switches, offering a higher levels-per-switch ratio. Moreover, they can also operate at a lower switch blocking voltage. These features offer an interesting cost–benefit and make them attractive options to industry applications. The system model, modulation technique, and control strategy are discussed. Simulation and experimental results are provided in order to validate their performance and feasibility.

Block Switching: A Stochastic Approach for Deep Learning Security

Recent study of adversarial attacks has revealed the vulnerability of modern deep learning models. That is, subtly crafted perturbations of the input can make a trained network with high accuracy and produce arbitrary incorrect predictions, while maintaining imperceptible to human vision system. In this paper, we introduce Block Switching (BS), a defense strategy against adversarial attacks based on stochasticity. BS replaces a block of model layers with multiple parallel channels, and the active channel is randomly assigned in the run time, hence unpredictable to the adversary. We show empirically that BS leads to a more dispersed input gradient distribution and superior defense effectiveness compared with other stochastic defenses such as stochastic activation pruning. Compared to other defenses, BS is also characterized by the following features: (i) BS causes less test accuracy drop; (ii) BS is attack-independent; and (iii) BS is compatible with other defenses and can be used jointly with others.

FPGA Hardware in the Loop Validation of Asynchronous Machine with Full Direct Torque Control Implementation

This article provides a full hardware implementation for direct torque control (DTC) of an asynchronous motor (AM) on the Field Programmable Gate Array (FPGA). Due to its high processing frequency, the FPGA circuit presents an alternative for achieving a high performance DTC implementation. This cannot be achieved by any DSP or microcontroller application. The proposed hardware architecture implements three components of DTC control strategy (the integral proportional speed regulator, the estimation and the switching blocks). This implementation has the advantage of being faster, more efficient and with minimum hardware resources on the target FPGA board. The hardware architecture of the DTC control was designed and simulated in Matlab / Simulink using XSG blocks, then synthesized with the Xilinx ISE 14.2 tool, implemented and validated on the Xilinx Virtex-4 FPGA circuit by Hardware in the Loop process.

Sliding-Mode-Based Current and Speed Sensors Fault Diagnosis for Five-Phase PMSM

The present paper deals with an active fault-tolerant speed tracking of a five-phase permanent magnet synchronous motor with currents and speed sensor failures. The active fault tolerant control scheme, integrating a sliding mode observer and backstepping controllers, is proposed to provide a continuous drive operation of the five-phase permanent magnet synchronous motor, even during more than one sensor fault occurrence. The sliding mode observer is designed to generate the residual signal necessary for the detection stage, whereas speed and current backstepping controllers handle the operation of the five-phase permanent magnet synchronous motor thanks to their ability to consider the nonlinearities of the system model in generating a control law that is robust enough in healthy and faulty cases. Furthermore, the FTC strategy uses the information received from the fault-tolerant switching block in terms of the measured and the observed currents and speed signals. To gain the maximum benefit of the sliding mode observer’s robustness to random noises and its ease of implementation, the observed currents and speed of the five-phase permanent magnet synchronous motor have been estimated. The simulation results are conducted to show the effectiveness of the proposed FTC control scheme and to prove its high performance in fault detection and tolerant control for the five-phase permanent magnet synchronous motor, since it significantly outperforms the performance provided by traditional methods.

An Enhanced Electroporator Design for Pulse Generation

An electroporator is an instrument used for delivering electrical pulses to a tumor. In this work, an electroporator consisting of three main system blocks, namely High Voltage (HV) source, nanosecond (ns) switching, and pulse generation, was designed, developed, and evaluated to generate high voltage ns pulses to treat tumors. The high-voltage source block was used to convert the 9.6V DC from the battery to a variable HV output and store this charge for later use. The ns switching block contained a MOSFET-based low-side switch which applies short ns pulses to the load. The pulse generation block generates short ns pulses and supplies the adequate current to turn on the MOSFET at a quicker rate aiding the application of these pulses to the load. This process was simulated using PSpice software and the results are presented.

Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction

Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced by the use of a high resolution digital-to-time converter with its range and duty cycle calibration in background. Also, the nonlinearity of the analog front-end circuit in the proposed hearing aid SoC is reduced by introducing a switching block based dynamic element matching process. Furthermore, an improved noise reduction algorithm is proposed based on pitch based voice activity detector and multiband complex spectral subtraction to improve the performance of the proposed hearing Aid SoC. The proposed hearing aid SoC is designed in an 180 nm CMOS technology. The simulation results show that, integrated jitter of the proposed structure is reduced to 0.9 psrms and it achieves a signal to noise ratio of 89.24 dB. The total power consumption of this hearing aid is only 996 μW for 1.2 V supply that shows the superiority of the proposed work than existing works.

Reliability and economic feasibility analysis of parallel unity power factor rectifier for wind turbine system

High power rated modern wind generators are demanding immaculate performance and greater reliability from the power electronics interface. In order to keep up to the challenges, advanced multilevel front-end rectifiers and parallel operation of rectifiers are researched. A higher number of semiconductor switches make reliability estimation and feasibility of converters a factor of industrial interrogation. This study focuses on the operation, reliability, and economic feasibility analysis of a parallel unity power factor rectifier (PUPFR). Each branch of the PUPFR has a three-phase diode rectifier and each phase of which is equipped with bidirectional switching blocks. Suitability of uninterrupted operation with lower down-time for instances of one branch failure, the system discussed provides higher feasibility, reliability, and options of modularity. The reliability is assessed by quantifying the failure rate of each component of the converter topology. The feasibility analysis of the PUPFR focuses on quantitative evaluation based on component pricing for initial cost, maintenance, power-loss calculation, operational cost, and capacity factor. The PUPFR is comparatively assessed with respect to its single branch topology, i.e. the unity power factor rectifier. Both the topologies are simulated in MATLAB®/Simulink and the system is experimentally validated on a 1 kW hardware setup.

Effects of theta burst stimulation over the dorsolateral prefrontal cortex on language switching – A behavioral and ERP study

This study investigated the role of the left dorsolateral prefrontal cortex (DLPFC) in language switching using theta burst stimulation (TBS) and electroencephalography in late bilinguals. After a sham-controlled baseline, participants received either excitatory or inhibitory TBS over the left DLPFC before conducting picture naming tasks in pure language blocks and a language switching block, as well as a nonverbal switching task. On the behavioral level, we found no effect of TBS. However, the ERP-analysis revealed an effect of Stimulation for the picture naming tasks, characterized by alterations in the left DLPFC at 20–72 ms, and in networks associated with conflict resolution and self-monitoring at 533–600 ms. As we did not find an interaction between Stimulation and Block (switching vs non-switching), prefrontal stimulation did not specifically modulate interlanguage control. The left DLPFC might rather be involved in enhancingmaintenance of task demands and self-monitoring during language production in both mono- and bilingual contexts.

The Instructed Task-Switch Evaluation Effect: Is the Instruction to Switch Tasks Sufficient to Dislike Task Switch Cues?

It is often argued that people dislike situations in which there is conflict requiring cognitive control, possibly because it is effortful to resolve this conflict. In a recent study, Vermeylen, Braem, and Notebaert (2019) provided evidence for this idea in the context of task switching. They observed that participants evaluated cues signaling a task switch more negatively than cues signaling a task repetition in a task switching paradigm. The present study examined whether this evaluative bias can be observed also on the basis of mere instructions. We instructed participants that two non-words would either signal the requirement to switch or to repeat tasks in an upcoming task switching block, which was actually never administered. In Experiment 1, we did not observe more positive implicit or explicit evaluations of the instructed task repetition compared to the task switch cue. In Experiment 2, participants first completed a task switching block in which a first pair of transition cues were used. We then provided task switching instructions that described the signaling function of a second pair of cues, which would be used in an upcoming (but never administered) second task switching block. Participants showed a clear preference for both instructed and experienced task repetition cues on explicit but not on implicit evaluations. Experiment 3 replicated the instructed task-switch evaluation effect on explicit evaluations in the context of prior task experience (but not without prior experience) and extended it to implicit evaluations. We discuss theoretical implications and potential explanations of this task-switch evaluation effect.

중간 주파수 위상 스위칭을 이용한 UWB 선택적 단측파대 폴디드 캐스코드 쿼드러처 믹서

A folded-cascode single-sideband(SSB) quadrature mixer with an intermediate frequency(IF) input switching block has been proposed to reduce power dissipation and select frequency components for ultra-wideband applications. By changing each phase of the IF signals, the unwanted output spectrum(sum or difference) is removed selectively. The SSB mixer has been designed in the Samsung 65-nm RFCMOS process. From the simulated results, the SSB mixer exhibits a maximum conversion gain of 5 dB with an image signal rejection ratio of 45 dBc in 3.168～10.56 GHz. The SSB mixer operates at a supply voltage of 1.2 V with 1.7 mW power consumption.

The Effect of Exercise on Neural Activation in Older Adults

Acute exercise (EX) affects neural activation, assessed with functional magnetic resonance imaging (fMRI), and is a suggested mechanism in the effects of EX on behavioral measures of cognition. PURPOSE: We investigated the effect of EX on neural activation during a set switching task (SST). METHODS: Six healthy, right-handed older adults (M=71.4±5.1) completed two separate visits [EX; 30-min of cycling at 55-65%Heart Rate Reserve and rest (RS); 30-min of seated rest]. After EX or RS participants completed a SST during an fMRI. SSTs are a measure of executive function where participants shift attention between sets of rules during the task. Switch cost (cost) is the performance difference between switching (i.e. A, B, A) and repeat trials (i.e. A, A, A). The conditions included rest, a high switching block [70% switching, 30% repeat trials (HS)], and a low switching block [20% switching, 80% repeat trials (LS)]. fMRI analyses using FSL included assessment of main effects of activation during HS and LS blocks during EX and RS and a comparison of activation with reaction time cost. RESULTS: Across both HS and LS and EX and RS, participants similarly activated the lateral occipital cortex and frontopolar area. In addition, there was significant activation of the superior and inferior frontal gyri, middle frontal gyrus, cerebellum VIIb, thalamus, caudate, and insula following RS in HS and LS. There were no unique areas of activation in HS following EX, however in LS there was activation in the temporal occipital fusiform gyrus, inferior frontal gyrus, and middle frontal gyrus. In relation to performance, cost during HS was associated with activation of the cerebellum VIIb following EX and activation of the thalamus and occipital pole following RS. Further, cost during LS was associated with activation in the frontopolar area after EX and activation in the thalamus following RS. CONCLUSION: Similar activation during HS and LS following rest and EX suggests a common network for SSTs. During the HS blocks, EX did not elicit additional unique activation, as seen following RS or the LS block, suggesting EX-induced efficiency. More research is needed to better understand the implication of differential activation. Results presented at ACSM will include additional participants; findings and conclusions will reflect the final analyses.