Switching Activity Research Articles

Design Of Modified Data Driven Clock Gating And Look Ahead Clock Gating For Low Power

Clock signal is considered as an immense source of power dissipation in synchronous circuits because of large frequency and load. It does not carry any information but consumes high power at the switching activity which is to be avoided. So, by using clock gating we can save power by reducing unnecessary transition activity inside the gated module. Hence modified design of data driven clock gating and look ahead clock gating is designed to obtain the less power in the circuits. These two techniques are compared among them and by the results obtained through cadence virtuoso tool we can conclude that look ahead clock gating consumes low power, low noise response and higher performance.

Test Power Reduction by Simultaneous Don’t Care Filling and Ordering of Test Patterns Considering Pattern Dependency

Estimating and minimizing the maximum power dissipation during testing is an important task in VLSI circuit realization since the power value affects the reliability of the circuits. Therefore during testing a methodology should be adopted to minimize power consumption. Test patterns generated with –D 1 option of ATALANTA contains don’t care bits (x bits). By suitable filling of don’t cares can minimize the number of switching activity between two successive patterns. The switching power dissipation of the Circuit under Test (CUT) also depends on the order of patterns applied for. If consecutive pattern application time is sufficiently large then leakage power dissipation does not alter on the ordering of the patterns. So under this circumstances leakage power does not change but if the pattern application time is small leakage power depends on the ordering of the pattern applied to the CUT. Previous works concerns only about don’t care filling or pattern ordering or first filling of don’t care and then ordering for low power circuit testing. Ordering after filling of don’t care may change the benefits of X-filling. The advantage of test power reduction of both the methods - don’t care filling and ordering may be obtained if they are considered together. In this work an approach based on Genetic Algorithm (GA) is used to solve the integrated problem for X-filling and reordering of test patterns considering pattern dependency to minimize the switching activity throughout testing without changing the fault coverage. Effectiveness of the proposed GA based approach compared to existing approach considering test patterns for ISCAS’85 benchmark circuits is shown in the result section.

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

SummaryThis paper presents redundancy‐bandwidth scalable techniques to deal with the intersymbol interference distortions for current‐steering digital‐to‐analog converters in high‐speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal‐independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high‐speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy‐bandwidth scalable trade‐offs between the cost from redundant current sources and the high‐dynamic‐range bandwidth. In implementation, we propose a custom‐designed decoder, named as the overlap‐controlled data‐weighted averaging (OC‐DWA). Compared with the existing similar‐purpose designs, the proposed OC‐DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption. Simulations of a digital‐to‐analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy‐bandwidth scalability of the proposed techniques.

Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection

Soft errors produced by radiation events can cause malfunctions in modern day electronics. To preserve the system functionality, its elements must be protected against the effects of these events. Two of the possible techniques usually employed to implement fault tolerant registers are triple modular redundancy (TMR) and single error correcting (SEC) codes. However, the use of these techniques increases circuit area, timing, and power consumption to different extents. In this paper, we study the influence of each of these approaches on the circuit when they are implemented in application-specific integrated circuits and, based on the results, present some guidelines to choose between both of them depending on the design requirements. Additionally, we present a new low power fault tolerant technique destined for registers in which a subset of bits have a lower switching activity than the rest. This approach is based on the idea of combining TMR and SEC codes within a register to implement a hybrid protection that can exploit the strengths of each of the techniques. Our results show that the use of this technique achieves both power and area savings with respect to TMR in most cases, whereas it achieves large power savings with respect to SEC codes at the cost of increasing the area overhead.

Functional-power-aware Partial Gating Method for Low Power Scan-shift

This paper presents a new scheme to minimize scan-shift power for test reliability with minimized functional power overhead, which is achieved by selective insertion of signal gating-logic considering the loading condition and switching activity of scan shift signals. The proposed methodology also considers practical design issues such as logic-timing overhead and cell-congestion impact associated with scan-shift power reduction. In experimental results with industrial system-on-chip (SoC) designs, the proposed power-aware gatinglogic- insertion methodology not only achieved reduction of scan-shift power but also improved functional power up to 10% compared with the conventional full-scan gating scheme.

Clock node capacity minimization using lookup table based controller for ultrasound and medical imaging processor

Low power system on-chip design without performance degradation is the most critical design issue for the processor involved in medical image diagnosis. To make the medical device portable, it is necessary to reduce the processor size with less power consumption. The performance of the chip is affected drastically due to rise in temperature produced by unnecessary internal switching. Hence it is necessary for power optimization and minimizing unnecessary switching. In our proposed work, an efficient level shifting scheme of clock signal can be achieved by utilizing lookup table based level conversion scheme in clock node. The switching activity is verified for various logic network using multi-level conversion scheme with Conditional Capture technique and Improved Conditional Capture technique. It ensures the power saving by turning on a functional logic block only when required and minimizes the unnecessary clock node activity. This paper analyzes the proposed work in 0.6 \(\upmu \)m, 50 n CMOS processor and compares the results with the existing power and delay optimization techniques as it is widely applicable for image analysis.

Biochemical Studies and Molecular Dynamic Simulations Reveal the Molecular Basis of Conformational Changes in DNA Methyltransferase-1.

DNA methyltransferase-1 (DNMT1) plays a crucial role in the maintenance of genomic methylation patterns. The crystal structure of DNMT1 was determined in two different states in which the helix that follows the catalytic loop was either kinked (designated helix-kinked) or well folded (designated helix-straight state). Here, we show that the proper structural transition between these two states is required for DNMT1 activity. The mutations of N1248A and R1279D, which did not affect interactions between DNMT1 and substrates or cofactors, allosterically reduced enzymatic activities in vitro by decreasing kcat/ Km for AdoMet. The crystallographic data combined with molecular dynamic (MD) simulations indicated that the N1248A and R1279D mutants bias the catalytic helix to either the kinked or straight conformation. In addition, genetic complementation assays for the two mutants suggested that disturbing the conformational transition reduced DNMT1 activity in cells, which could act additively with existing DNMT inhibitors to decrease DNA methylation. Collectively, our studies provide molecular insights into conformational changes of the catalytic helix, which is essential for DNMT1 catalytic activity, and thus aid in better understanding the relationship between DNMT1 dynamic switching and enzymatic activity.

Design and Performance Analysis of High Speed Optical Binary Code Converter using Micro-Ring Resonator

ABSTRACTThe present paper describes various attractive logical code conversions using optical micro-ring resonator. We have proposed an all-optical switching activity using silicon waveguide based micro-ring resonator under low-power operation through two-photon absorption effect. The different properties of the optical switch are analyzed through numerical simulation. We have also proposed and described all-optical binary-to-octal, binary-coded-decimal-to-excess-3 and binary-to-Gray-code converter circuits by this proposed architecture. Numerical simulation results for code conversion verifying the proposed methods are given in this paper. We identify a combination of feasible ring radius and detuning through numerical simulation that allows analyzing the system performance of the scheme.

Optimized gate driver for high-frequency buck converter

With the increasing system complexity in the automotive business sector the integration of efficient and low electromagnetic emission (EME) switch mode power supplies (SMPS) is crucial. The main methods to bring down EME and keep high efficiency are to introduce external filters on the input and output sides, to use spread spectrum techniques on the switching frequency and to control the switching activity of output driver in the desired range. This paper presents the concept of output driver implementation with adaptive driver strength control and dead time optimization for high frequency buck converters with external power MOSFETs. The proposed concept allows the following characteristics to be achieved: improved control of switching activity in a closely defined range, efficiency optimization by minimization the body diode forward conduction, reduction of the reverse recovery losses and zero voltage switching. All these can be realized despite the unknown MOSFET technological parameter distribution (propagation on/off delay, gate resistance of the package, Miller gate charge) and the external parameters (temperature, input voltage, load current). The proposed concept was implemented for a 1.2 V output voltage and a 1.8 MHz switching frequency buck converter.

KAPow

In an FPGA system-on-chip design, it is often insufficient to merely assess the power consumption of the entire circuit by compile-time estimation or runtime power measurement. Instead, to make better decisions, one must understand the power consumed by each module in the system. In this work, we combine measurements of register-level switching activity and system-level power to build an adaptive online model that produces live breakdowns of power consumption within the design. Online model refinement avoids time-consuming characterization while also allowing the model to track long-term operating condition changes. Central to our method is an automated flow that selects signals predicted to be indicative of high power consumption, instrumenting them for monitoring. We named this technique KAPow, for ‘K’ounting Activity for Power estimation, which we show to be accurate and to have low overheads across a range of representative benchmarks. We also propose a strategy allowing for the identification and subsequent elimination of counters found to be of low significance at runtime, reducing algorithmic complexity without sacrificing significant accuracy. Finally, we demonstrate an application example in which a module-level power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by up to 7%.

A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm

This paper introduces a computationally efficient hardware architecture for reconfigurable multiple constant multiplication block, which functions according to the canonical signed digit (CSD)-based vertical and horizontal common sub-expression elimination (VHCSE) algorithm. In the proposed architecture, the CSD decoded coefficient along with 4-b common sub-expressions (CSs) in the vertical direction and 4- and 8-b CSs in the horizontal direction reduces the required number of full adder cells and the adder depths. This technique helps in reducing area consumption by decreasing the number of coefficient multiplier adders by 59% than that of the binary VHCSE (VHBCSE) algorithm. This technique helps in reducing the average switching activity of the adder blocks used in each coefficient multiplier block by 26.1%, 25.6%, and 21.3%, while compared with those of the 2- and 3-b binary CS elimination (BCSE) and VHBCSE algorithms, respectively. For different orders of filter, the proposed one delivers 57.5% and 61.9% improvement in area-power product (APP) on an average compared with the VHBCSE and mixed integer programming algorithms, respectively. Experimental results of differently specified finite impulse response (FIR) filters ranging from 10 to 100 taps and the coefficients of 8, 12, and 16 b show the improvements of 42.8%, 53.6%, and 37%, respectively, in the average gate count and 51.8%, 43.5%, and 36.7% less propagation delay than those of earlier canonical double-based number representation method. Moreover, in the metric made of APP divided by throughput, the proposed technique experiences 63.7% improvement on an average over that of faithfully rounded truncated multiple constant multiplication/accumulation technique of designing constant multiplier and demonstrates its suitability for implementing efficient reconfigurable FIR filter.

An Adaptive Low Power Coding Scheme for the NOC

Low power system design is important for system-on-chip design where communication takes place at higher data rate to realise the system functionality. Low power coding reduces energy by reducing self-switching activity or coupling switching activity. But under typical network-on-chip (NOC) system, we require a low power coding scheme to handle different kinds of data traffic from different IP core at different instant and different places in system-on-chip (SOC). As single low power coding scheme will not solve all application demands, a correlation analysis based adaptive data coding scheme is presented. Based on the classification of data traffic as low, moderate and highly correlated, different coding scheme is applied. The proposed system is simulated in labVIEW FPGA tool for the USRP RIO target. Based on comparative analysis of power consumption between the existing coding schemes and proposed adaptive scheme 25% energy saving is achieved at the worst case scenario.

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-μm CMOS

This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: skip-reset, delta ( $\Delta$ ) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but also digital switching energy for the ADC reset. The $\Delta$ -readout process with the proposed MSB-rounding technique shifts the location of the resolvable range using the previous digital code to increase the hit-rate. Finally, the tri-level split monotonic switching scheme minimizes the CDAC switching activity in predictive residue generation for the $\Delta$ -readout process. A prototype ADC was fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies an active area of 0.17 mm2. At a 1.5-V supply voltage and a 1-kS/s sampling-rate with the electrocardiogram signal input, the ADC power consumption could be reduced to 18.5 nW, corresponding to 71% power saving, and owing to the proposed techniques from a conventional SAR ADC consuming 63.5 nW.

The Influence of Acute Stress on Brain Dynamics During Task Switching Activities

Task switching is a common method to investigate executive functions such as working memory and attention. This paper investigates the effect of acute stress on brain activity using task switching. Surprisingly few studies have been conducted in this area. There is behavioral and physiological evidence to indicate that acute stress makes the participants more tense which results in a better performance. In this current study, under stressful conditions, the participants gave quick responses with high accuracy. However, unexpected results were found in relation to salivary cortisol. Furthermore, the electroencephalogram results showed that acute stress was pronounced at the frontal and parietal midline cortex, especially on the theta, alpha, and gamma bands. One possible explanation for these results may be that the participants changed their strategy in relation to executive functions during stressful conditions by paying more attention which resulted in a higher working memory capacity which enhanced performance during the task switching.

Fault detection and analysis of bistable rotaxane molecular electronic switch - A simulation approach

ABSTRACTAs the transistor size approaches nano dimension, short channel effects become dominant in micro devices, leading to an incessant struggle to keep pace with Moore's law. This paved way to development of newer technologies like molecular electronics. The self-assembled bottom-up approach makes molecular switches more prone to defects than micro devices. The widely studied molecular switches are mechanically coupled and this paper deals with bistable rotaxane. Feasibility of using bistable rotaxane as a molecular electronic device is analysed in terms of total molecular energy, energy band gap, ionisation energy and distance between ring and dumbbell. Total molecular energy is the vital criteria that decides the feasibility of using a self-assembled rotaxane as a switch. Rotaxane has a band gap of 1.44 eV at Ground State Co-Conformer (GSCC) and hence acting as a semiconductor. Ionisation energy and position of ring are also important in deciding the switching activity. Due to process variations during self-assembly, ring can localise anywhere over the dumbbell and it may leads to a faulty switch. This work describes a method to verify the switching action of bistable rotaxane through simulation. Testing method described here is carried out before the actual manufacturing of nano crossbar and hence cost effective.

Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point

This paper introduces a transregional energy model to estimate the energy consumption of digital designs for voltages widely ranging from nominal down to deep sub-threshold. The model also predicts the optimal voltage at which the minimum energy point (MEP) occurs, and the resulting minimum energy achievable under aggressive voltage scaling. The model provides the energy profile versus voltage based on a few technology-dependent parameters that are extracted through simple circuit simulations, and other few design-dependent parameters extracted from synthesis or Place&Route reports at nominal voltage only. The model captures the effect of input-dependent (e.g., switching activity), technology-dependent (e.g., corner, transistor flavor), and micro-architectural parameters (e.g., logic depth). The model exhibits a typical error below 10%, and is well suited for design exploration under wide voltage scaling, as it avoids detailed and time-consuming multi-corner and multi-voltage iterations. Also, the model provides a quick estimate of the achievable MEP for a given design. Accordingly, the proposed model is a useful tool that supports early selection of the most energy-efficient design options to meet a targeted energy profile at low voltages.

Close-to-Functional Broadside Tests With a Safety Margin

Scan-based tests that maintain close-to-functional operation conditions are important for avoiding overtesting of delay faults while achieving the fault coverage required for avoiding test escapes. For a measurable proximity to functional operation conditions, partially functional broadside tests have a known Hamming distance between their scan-in states and reachable states. Another parameter that is important for the discussion of overtesting is the switching activity. This paper suggests a combined metric, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state. The metric is defined such that a value of 100% or lower is preferred. To demonstrate that the metric is flexible enough to allow tests to be generated, the paper describes a test generation procedure that uses the metric.

Fully Integrated Inductor-Less Flipping-Capacitor Rectifier for Piezoelectric Energy Harvesting

This paper presents a fully integrated piezoelectric energy harvesting interface without external components. Instead of relying on bulky external inductors with high quality factor as in the conventional parallel-synchronized-switch harvesting-on-inductor (P-SSHI) approach, we propose a flipping-capacitor rectifier (FCR) topology to achieve voltage inversion of the piezoelectric energy harvester through a reconfigurable capacitor array. This fundamentally preserves a fully integrated solution without inductors while achieving a high-energy extraction capability. Measurement results from FCR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> using discrete components shows an output power enhancement of up to 3.4×, which is close to the theoretical prediction. We also fabricated a sevenphase FCR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> with four MIM capacitors and 21 switches using a 0.18-μm 1.8/3.3/6 V CMOS process, occupying an active area of ~1.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Additionally, we implemented an active rectifier based on a common-gate comparator with phase alignment to ensure high-speed operation while minimizing the diode voltage drop. A phase generate-and-combine circuit eliminates redundant switching activities. Systematic optimization of the three main energy loss mechanisms during the finite flip time: 1) phase offset; 2) incomplete charge transfer; and 3) reduced conduction time, is also introduced. Measurement results show that the output power enhancement can reach up to 4.83× at an excitation frequency of 110 kHz.

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

In this paper, an ultralow-power true single-phase clocking flip-flop (FF) design achieved using only 19 transistors is proposed. The design follows a master–slave-type logic structure and features a hybrid logic design comprising both static-CMOS logic and complementary pass-transistor logic. In the design, a logic structure reduction scheme is employed to reduce the number of transistors for achieving high power and delay performance. Despite its circuit simplicity, no internal nodes are left floating during the operation to avoid leakage power consumption. In this design, a virtual $V_{{\mathrm{DD}}}$ design technique, which facilitates a faster state transition in the slave latch, is devised to enhance time performance. In circuit implementation, transistor sizes are optimized with respect to the power-delay product (PDP). A TSMC 90-nm CMOS process was selected as the implementation technology. In this paper, the performance levels of seven FF designs were compared. The timing parameters of each FF were first characterized. Post-layout simulation results indicated that the proposed design excelled in various performance indices such as PDP, clock-to-Q delay, average power consumption, and leakage power consumption. Moreover, the design was determined to have the smallest layout area. Compared with the conventional transmission-gate-based FF design, the PDP improvement in the proposed design was up to 63.5% (at 12.5% switching activity) and the area saving was approximately 10%. Further simulations on process corners, supply voltage settings, and working frequencies were conducted to study the design reliability.

Why Consumers Switch Energy Suppliers: The Role of Individual Attitudes

ABSTRACT Since 2008, fewer customers switched suppliers in British electricity and gas markets despite the potential for financial gains, suggesting that psychological factors may affect switching behaviors. Using a unique nation-wide British survey, we explore the influence of consumers’ attitudes and perceptions on switching behaviors and assess the differences in switching propensity across different groups. Support for simplifying energy tariffs, professed less difficulty in understanding energy bills, expected difficulty in changing suppliers and lack of attention to the issue of energy prices are associated with lower switching activity. At a time of high saliency, political party voting intention was strongly related to switching. Unlike the bivariate analyses conducted by the regulator and the competition authority, our multivariate analysis show few demographic factors affect the likelihood of switching except for educational attainment and tariff payment patterns. Remedies aiming to encourage switching cannot be targeted correctly unless the supporting analysis is robust to alternative model specifications.