Switch-mode Power Amplifier Research Articles

Taking Advantage of the Sum of the Light in Outphasing Technique for Visible Light Communication Transmitter

Visible light communication (VLC) takes advantage of the widespread use of the light-emitting diodes (LEDs), and by modifying the driver stage, the LEDs are capable of lighting and transmitting information. One of the main drawbacks is the low power efficiency due to the modification of the LED driver stage in order to add the communication capability. Most of the research work related to VLC is toward the communication task, whereas there is a limited work about the improvement on power efficiency. This article proposes a high-efficiency LED driver for VLC working as a transmitter based on the outphasing technique. This technique is used also in radio frequency (RF) communications and increases the efficiency of the amplifiers. The proposed transmitter is made up of two switching-mode power amplifiers that reproduce the signals required for the outphasing technique and a dc/dc converter that biases the LEDs. The proposal exploits the light and, instead of being added electrically, the signals are added in their light form, which leads to a reduction in the complexity of the design. As experimental results, a transmitter was built of two Class E amplifiers reproducing a 16-QAM modulation, achieving a signal-generation efficiency of 78% and an overall efficiency of 92%.

A Class D Power Amplifier for Multifrequency Eddy Current Testing Based on Multisimultaneous-Frequency Selective Harmonic Elimination Pulsewidth Modulation

Efficiency and multisimultaneous-frequency (MSF) output capability are two major criteria characterizing the performance of a power amplifier in the application of multifrequency eddy current testing (MECT). Switch-mode power amplifiers are known to have a very high efficiency, yet they have rarely been adopted in the instrumental development of MECT. In addition, switch-mode power amplifiers themselves are lacking in the research literature for MSF capability. In this article, a Class D power amplifier is designed so as to address the two issues. An MSF selective harmonic elimination pulsewidth modulation method is proposed to generate alternating magnetic fields, which are rich in selected harmonics. A field-programmable-gate-array-based experimental system has been developed to verify the design. Results show that the proposed methodology is capable of generating high MSF currents in the transmitting coil with a low distortion of signal.

Optimal Energy Characteristics and Working Parametries of RF Switch Mode Power Amplifier Based on Controllable Current Fed Resonant Inverter

This article represents us the method for power losses minimizing in transistors of a radio frequency key gen-erator (power amplifying) based on the control method application with overlapping pulses. We see fully formed requirements for the optimal excitation mode, providing maximum efficiency and maximum operating frequency, taking into account the finite times of switching on and off the generator GaN transistors. The article shows the obtained analytical equations for calculating power in a load, loss of efficiency, as well as equations for estimating the maximum operating frequency of the generator depending on the permissible level of losses. The article presents graphics of curves that determine the maximum operating frequency of an RF generator for permissible switching losses on various types of GaN transistors.

Triple buck converter – an efficient low‐distortion switch‐mode power amplifier topology

A switch-mode power amplifier topology that can achieve both a high conversion efficiency and low-output signal distortion is introduced. Such systems are desirable for ultra-high precision amplifiers that, for example, drive actuators in nanometre-accuracy mechatronic positioning applications in integrated semiconductor manufacturing. An efficient Class-D power stage, which is limited in output signal quality due to its inherent half-bridge interlock time, is combined through a magnetically coupled inductor with a dual buck conversion stage that does not require interlock time and, due to its circulating bias current that defines the half-bridge switching waveforms, achieves very low-harmonic output signal distortion. The control system can seamlessly adjust the current sharing of the two converter stages such that overall conversion efficiencies over 95% and output total harmonic distortion values below −100 dB are achievable at power levels up to several kilowatts. Detailed computer simulations demonstrate the feasibility of the concept.

A Novel High-Pass Delta–Sigma Modulator-Based Digital-IF Transmitter With Enhanced Performance for SDR Applications

This brief presents a new transmitter architecture based on digital-intermediate frequency (IF) high-pass delta–sigma modulator (HPDSM). The proposed digital-IF transmitter topology utilizes a novel complex HPDSM topology to address the high quantization-noise power problem in Cartesian band-pass BPDSM and HPDSM-based digital-IF transmitters, without increasing the oversampling ratio of the signal or the clock rate of the system. To evaluate the performance of the new digital-IF transmitter system, a comparison with its Cartesian band-pass and high-pass counterparts, in terms of signal to noise and distortion radio (SNDR) and coding efficiency, was established. A simulation using 8 dB peak to average power ratio long term evolution signals with 1.24-MHz bandwidth showed that by integrating the proposed second-order complex HPDSM digital-IF in the transmitter, the power of the quantization noise is significantly reduced. The transmitter digital blocks were implemented on the BEEcube software-defined radio prototyping platform. The input signal is encoded by the new HPDSM topology and is up-converted and then fed to the inverse class-F switch-mode power amplifier. An overall efficiency of 12% was achieved by the proposed topology. Moreover, the output signal SNDR reached 37.8 dB and the adjacent channel leakage ratio at the lower and upper 1.25-MHz offset frequencies measured is equal to −35 dBc.

Theory and Implementation of a Load-Mismatch Protective Class-E PA System

Highly efficient switch-mode class-E power amplifiers (PAs) are sensitive to load impedance variations. For voltage standing wave ratios (VSWRs) up to 10:1, the peak switch voltage and the average switch current can increase by a factor of 1.7 and 2.5, respectively, relative to those under nominal load conditions, imposing serious reliability risks. This paper describes a technique to self-protect class-E PAs to decrease their sensitivity to load variations, relying on the tuning of the switch-tank relative-resonance frequency, implemented by an on-chip switched-capacitor bank (SCB). To validate the technique, load-pull measurements are conducted on a class-E PA implemented in a standard 65-nm CMOS technology, employing an off-chip matching network, augmented with a fully automated self-protective control loop. Under nominal conditions, the PA provides 17.8 dBm at 1.4 GHz into $50\,{\Omega }$ from a 1.2-V supply with 67% efficiency. The proposed self-protective PA can reduce its peak switch voltage below the technology- and switch design-related limit for any load with a VSWR up to 19:1 while not considerably impacting output power and efficiency, which see a maximum degradation of 1.6 dB and 6%, respectively. Furthermore, a class-E PA designed to safely handle $2.5{\times }$ the nominal average switch current can reliably operate for VSWRs up to 19:1 when protected with our technique.

Analysis and Design of High-Efficiency Parallel-Circuit Class-E/F Power Amplifier

In this paper, a single-ended parallel-circuit (PC) class-E/F power amplifier (PA) is proposed. For a particular case of the PC class-E/F3 mode with 50% duty cycle, its analytical derivation of the idealized waveforms, optimum values of the load network components, and significant figure-of-merit of PA is elaborated and verified. The ideal optimum voltage and current waveforms do not overlap simultaneously, which presents a theoretical drain efficiency of 100%. In addition, compared with other switch-mode PAs, the proposed structure successfully improves the performance in the peak drain voltage ( $V_{\mathrm {max}}$ ), maximum operating frequency ( $f_{\mathrm {max}}$ ), and power output capability ( $c_{p}$ ). Hence, it provides a good choice for high-efficiency mobile/wireless communication systems in the future. The analysis is validated by simulation and design of a test board. The measurement result shows the output power of 40.4 dBm, drain efficiency of 83.9%, power-added efficiency of 77.2%, and power gain of 10.4 dB at an operating frequency of 2.6 GHz.

Modulation Induced Current Imbalance and Its Sensorless Control of a GaN-Based Four-Phase DC–DC Power Amplifier

The development of wide band-gap semiconductor devices is rapidly promoting the development of power electronics technology, especially in high frequency (HF) power converter region. A category of HF power converter is switch-mode power amplifier (PA). This paper focuses on the implementation of a multiphase dc–dc PA with high bandwidth and high power rate. When naturally sampled phase-shifted carrier modulation is implemented in the practical digital control system to control this HF power converter, the pulsewidth error problem caused by limited domain frequency of control chip becomes much severer. As a result, dc voltage component of each phase becomes different under several conditions, leading to current imbalance among phase inductors. This paper analyzes this problem and proposes a sensorless control method to solve it, based on the injection of random sequence in reference wave. A four-phase prototype employing GaN devices is fabricated, switching at 1 MHz. Current imbalance and effectiveness of the proposed control method are verified by experimental results. The prototype is capable of uniformly amplifying sine signal within 200 kHz and a 350 kHz bandwidth random signal, with peak output power up to 810 W.

Power‐efficient aliasing‐free PWM transmitter

Linearity and efficiency are important parameters in determining the performance of any wireless transmitter. Pulse-width modulation (PWM) based transmitters offer high efficiency but suffer from low linearity due to image and aliasing distortions. Although the problem of linearity can be addressed by using an aliasing-free PWM (AF-PWM), these transmitters have a lower efficiency as they can only use linear power amplifiers (PAs). Moreover, an all-digital implementation of such transmitters is not possible. The aliasing-compensated PWM transmitter (AC-PWMT) has a higher efficiency due to the use of switch-mode PAs (SMPAs) but uses outphasing to eliminate image and aliasing distortions and requires a larger silicon area. In this study, the authors propose a novel transmitter that eliminates both aliasing and image distortions while using a single SMPA. The transmitter can be implemented using all-digital techniques and achieves a higher efficiency as compared to both AF-PWM and AC-PWM based transmitters. Measurement results show an improvement of 11.3, 7.2, and 4.3 dBc in the ACLR as compared to the carrier-based PWM transmitter (C-PWMT), AF-PWMT, and AC-PWMT, respectively. The efficiency of the proposed transmitter is similar to that of C-PWMT, which is an improvement of 5% over AF-PWMT.

An Equal-Area Criterion Based Pulse Encoding Strategy for RF Switch-Mode Power Amplifier

Abstract A novel pulse encoding strategy for RF switch-mode power amplifier (SMPA) is proposed in this paper to achieve benefits of multi-level delta-sigma modulators (DSM) while alleviating challenges that multi-level DSM brings to SMPA. The pulse encoder consists of a multi-level delta-sigma modulators (DSM) followed by a level transformation module (LTM). Based on the equal-area criterion, LTM directly maps the multi-level DSM pulse train into a binary pulse train which enables a simple system configuration. The feasibility and effectiveness of proposed strategy are verified by numerical simulation and experimental measurement. Results show that, with a similar coding efficiency, the proposed strategy obtains more than 7 dB improvement in average in-band signal to noise ratio (SNR) compared to traditional two-level DSM.

Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers

Digital transceiver architectures offer the potential for achieving wireless hardware flexibility to frequency and modulation scheme for future-generation communications systems. Additionally, digital transmitters lend themselves to the use of switch-mode power amplifiers, which can have significantly higher efficiency than their linear counterparts. Two proposed architectures for realizing digital transmitters will be described in this work, both of which employ a hybrid combination of silicon integrated circuits (IC) and a power technology (e.g. GaN). This hybrid architecture takes advantage of the silicon to implement the high-complexity signal processing required for wireless communications, and uses power devices with high power density and low parasitic capacitance to sufficiently amplify the RF signals for transmission. Unfortunately, interfacing the low-power RF switching signals with off-chip high-power devices poses numerous design challenges, including: generation of integrated silicon power drivers with sufficient voltage swing for controlling power devices such as GaN, mitigation of on-chip current transients, wideband assembly interface from the silicon IC to the power device, and full system design verification using multiple process technologies. This work presents two CMOS driver architectures that can be used to interface low-power CMOS processing circuits with off-chip high-power devices. This work also details the performance limitations when assembling and interfacing multiple process technologies that are not co-located on the same IC. The main function of the driver circuitry within the digital transceiver system is to interface the low-power digital modulator to a large, high capacitance, off-chip power device. The driver must provide adequate transient current to charge/discharge the off-chip power devices' input capacitance through parasitic routing. Furthermore, the driver is designed to exhibit rise/fall times of less than 5% of the switching period and low jitter to meet RF signal quality requirements. Since silicon process technologies typically have much lower voltage breakdowns than those required to drive a power devie (e.g. GaN device), special driver architectures must be implemented to ensure the CMOS devices never exceed their breakdown voltages. Two architectures were implemented within this work to simultaneously achieve RF switching speeds and 5V signal swing from a 0.9V silicon CMOS process technology. The two architectures are: 1) a House-of-Cards configuration, and 2) a Cascode topology. These architectures will be detailed and compared with respect to performance in this presentation. Two of the most common techniques to assemble and connect a silicon IC, which includes the driver circuitry, and a (GaN) power device are: 1) direct wire bonding or flip-chip connection from the IC to the GaN, and 2) connection through a board or package interface circuit. Since most high-performance RF power devices such as GaN have negative threshold voltage, the driver (CMOS) IC must either: 1) have a supply and ground that are shifted to negative voltage values, or 2) decouple the IC's output from the GaN device's input in order to properly control the GaN. Off-chip decoupling is more easily implemented, but may limit maximum operating frequencies due to the added interface network and board/module parasitics. This work shall detail the interface models and compare the assembly procedures and potential performance limits when using both of these most common assembly techniques.

Stability of a Switched Mode Power Amplifier Interface for Power Hardware-in-the-Loop

Power hardware-in-the-loop (PHIL) is an attractive, real-time system testing and validation technique. Virtual models can be replaced with physical equipment to emulate system integration testing, and perform model validation without the cost and risk of a full scale power system. Power amplifiers are the principal components that facilitate the power interface between the physical and the virtual systems. This necessary interfacing introduces dynamics that do not exist in the real system and is the source of stability and accuracy issues affecting PHIL applications. This paper presents a stability analysis of a practical PHIL system based on the ideal transformer model interface algorithm that utilizes a voltage source converter for power amplification. A systematic approach to evaluate the expected stability characteristics of PHIL experiments is developed. The analysis in this paper shows that in a practical system, the power amplifier's filter, sampling, and measurement filtering are all shown to influence the stability in a counterintuitive way, leading to a nonmonotonic stability characteristic. An experimental PHIL platform based on a real-time digital simulator real-time computer has been used to validate the analysis and confirm the effects of the practical interface. Switching dead-time is also shown to have a significant stabilizing effect.

Design of class-E power amplifier for capacitive power transfer system

High frequency power source is an indispensable part of capacitive power transfer system, and its performance plays an essential role in the overall system. Considering that class-E power amplifier is a prominent switched-mode power amplifier, and its power conversion efficiency can reach nearly 100%, theoretically. In this work, according to the requirements of capacitive power transfer system for power, the high efficiency class-E power amplifier as the AC source of the system has been designed. Firstly, the partial component parameters of class-E power amplifier can be calculated by circuit theory. Secondly, simulation circuits of the class-E power amplifier are designed by ADS software. Finally, an experimental prototype with the designed parameters is built up to verify the theory and simulation results. The experimental results show that the improved class-E power amplifier can reach work efficiency of 91% with 30 W output power, and capacitive power transfer system can achieve transfer efficiency of 76.2% with 25.15 W output power.

Three-Level De-Multiplexed Dual-Branch Complex Delta-Sigma Transmitter.

In this paper, a dual-branch topology driven by a Delta-Sigma Modulator (DSM) with a complex quantizer, also known as the Complex Delta Sigma Modulator (CxDSM), with a 3-level quantized output signal is proposed. By de-multiplexing the 3-level Delta-Sigma-quantized signal into two bi-level streams, an efficiency enhancement over the operational frequency range is achieved. The de-multiplexed signals drive a dual-branch amplification block composed of two switch-mode back-to-back power amplifiers working at peak power. A signal processing technique known as quantization noise reduction with In-band Filtering (QNRIF) is applied to each of the de-multiplexed streams to boost the overall performances; particularly the Adjacent Channel Leakage Ratio (ACLR). After amplification, the two branches are combined using a non-isolated combiner, preserving the efficiency of the transmitter. A comprehensive study on the operation of this topology and signal characteristics used to drive the dual-branch Switch-Mode Power Amplifiers (SMPAs) was established. Moreover, this work proposes a highly efficient design of the amplification block based on a back-to-back power topology performing a dynamic load modulation exploiting the non-overlapping properties of the de-multiplexed Complex DSM signal. For experimental validation, the proposed de-multiplexed 3-level Delta-Sigma topology was implemented on the BEEcube™ platform followed by the back-to-back Class-E switch-mode power amplification block. The full transceiver is assessed using a 4th-Generation mobile communications standard LTE (Long Term Evolution) standard 1.4 MHz signal with a peak to average power ratio (PAPR) of 8 dB. The dual-branch topology exhibited a good linearity and a coding efficiency of the transmitter chain higher than 72% across the band of frequency from 1.8 GHz to 2.7 GHz.

A Modified All-Digital Polar PWM Transmitter

This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio.

Realization of a Power-Efficient Transmitter Based on Integrated Artificial Neural Network

In wireless devices, a transmitter normally consumes most of power due to its power amplifier (PA), especially in the applications such as radar, base station, and mobile phone. It is highly desirable to design a transmitter that can emit signals smartly, i.e., the power emission is exactly based on the emitting distance required and the target. Such a design can save huge amount of power as there are almost countless wireless devices in use currently. In this paper, an intelligent radio-frequency transmitter integrated with artificial neural network (ANN) is implemented. The intelligent transmitter consists of an ANN module, a frequency generation module, and a switch-mode PA. The integrated three-layered fully connected ANN can be offline trained to smartly classify input data according to the required power and assign the transmission channel. Furthermore, with the integrated ANN, the average power consumption of the PA is reduced to 34.3 mW, which is 46.5 % lower than PA without the ANN. With the intelligent transmitter, wireless devices can save a large amount of energy in their operations.

A Portable Ultrasound System for Non-Invasive Ultrasonic Neuro-Stimulation.

Fundamental insights into the function of the neural circuits often follows from the advances in methodologies and tools for neuroscience. Electrode- and optical- based stimulation methods have been used widely for neuro-modulation with high resolution. However, they are suffering from inherent invasive surgical procedure. Ultrasound has been proved as a promising technology for neuro-stimulation in a non-invasive manner. However, no portable ultrasound system has been developed particularly for neuro-stimulation. The utilities used currently are assembled by traditional functional generator, power amplifier, and general transducer, therefore, resulting in lack of flexibility. This paper presents a portable system to achieve ultrasonic neuro-stimulation to satisfy various studies. The system incorporated a high voltage waveform generator and a matching circuit that were optimized for neuro-stimulation. A new switching mode power amplifier was designed and fabricated. The noise generated by the power amplifier was reduced (about 30 dB), and the size and weight were smaller in contrast with commercial equipment. In addition, a miniaturized ultrasound transducer was fabricated using Pb(Mg1/3Nb2/3)O3-PbTiO3(PMN-PT) 1-3 composite single crystal for the improved ultrasonic performance. The spatial peak temporal average pressure was higher than 250 kPa in the range of 0.5-5 MHz. In vitro and in vivo studies were conducted to show the performance of the system.

A Stable and Fast-Transient Performance Switched-Mode Power Amplifier for a Power Hardware in the Loop (PHIL) System

Power Hardware in the Loop (PHIL) systems are used to test a power system with the help of combined software and hardware. Generally, to construct a PHIL system, a switched-mode power amplifier that has a stable performance is used, because of their large, linear signal control-to-output characteristics. However, the fundamental limitations of a switch-mode power amplifier (PA) are the dynamic performance and output bandwidth. In this paper, a compound controller has been used for the rectifier part of a PA, which can ensure the stability of a PA under transient or fault operating conditions. Moreover, a compound controller, which involves a feed-forward controller, a proportional controller and a repetitive controller, is proposed in the inverter part of a PA, and it can be used for PHIL applications. Experimental results are obtained under various operating conditions, such as transient responses under load step change, and output voltage bandwidth testing for a PHIL system, it is concluded that a proposed switched-mode power amplifier is useful for the PHIL system.

A 152-GHz OOK Transmitter With 3-dBm Output Power in 65-nm CMOS

A high output power 152 GHz ON-OFF keying transmitter in 65-nm CMOS is presented. The transmitter consists of a high dc-RF efficiency push-push voltage-controlled oscillator followed by a high-speed and high-gain switched-mode power amplifier. The transmitter achieves the highest output power (3 dBm) beyond 140 GHz in silicon process, with high on-off ratio (>39 dB) and high dc-RF efficiency (3.7%). The transmitter could support 10-Gb/s data rate communication with a bit-error rate of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> .

Hybrid inverter concept for extreme bandwidth high‐power AC source

A hybrid inverter concept for switch-mode power amplifiers as used, e.g. in power-hardware-in-the-loop testing is proposed. A main converter operating from the supplying DC voltage generates a multilevel output voltage by means of parallel-interleaved operation of several bridge legs and combination of the bridge leg output voltages with coupled inductors into a multilevel waveform. A second, series-connected inverter features a floating DC bus with only a fraction of the main converter's DC voltage, which enables a significantly higher switching frequency. The series inverter compensates the deviation of the main inverter's multilevel output voltage from the reference voltage, whereby pulse-width modulation with sawtooth carriers is employed, and hence defines the effective switching frequency of the hybrid inverter's overall output voltage. This allows for a higher output filter cutoff frequency and ultimately features a significant increase of the full-range system bandwidth, which improves by more than an order of magnitude for the considered 100 kVA example system compared with a conventional approach. Finally, closed-loop circuit simulations verify the high performance of the proposed system.