Limited by 4battery capacity, advanced microcontroller units (MCUs) for Internet of Things (IoT) applications require ultra-low power consumption. In a conventional design, the sleep power accounts for most of the total power consumption, and cannot be reduced further due to the low power efficiency of dc–dc converters at the load current ~100 nA. Voltage stacking has been proposed to address power efficiency. However, prior voltage-stacking architectures could not realize dynamic switching between flat mode and stack mode, leading to high dynamic power consumption in the normal state. This article proposes a dynamic voltage-stacking scheme, which supports two operating modes: a flat mode in the normal state and a stack mode in the sleep state. In the flat mode, the retention memories, RTC and XO32, are connected in parallel and are powered by the switched-capacitor voltage regulator (SCVR). In the stack mode, the four instances are connected in series, including the static random access memory (SRAM1) (level1), the SRAM2 (level2), and the XO32 and the RTC (level3), and the on-chip SCVR is shut down for power saving. The measurements show that compared with the conventional flat architecture, the dynamic voltage-stacking scheme reduces the sleep current by 38% under the same circumstances, and it also improves ULPMark-CP score by 23.6%, which is higher than the top1 in the ULPMark score list.