Switched-capacitor Voltage Regulator Research Articles

SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU

Limited by 4battery capacity, advanced microcontroller units (MCUs) for Internet of Things (IoT) applications require ultra-low power consumption. In a conventional design, the sleep power accounts for most of the total power consumption, and cannot be reduced further due to the low power efficiency of dc–dc converters at the load current ~100 nA. Voltage stacking has been proposed to address power efficiency. However, prior voltage-stacking architectures could not realize dynamic switching between flat mode and stack mode, leading to high dynamic power consumption in the normal state. This article proposes a dynamic voltage-stacking scheme, which supports two operating modes: a flat mode in the normal state and a stack mode in the sleep state. In the flat mode, the retention memories, RTC and XO32, are connected in parallel and are powered by the switched-capacitor voltage regulator (SCVR). In the stack mode, the four instances are connected in series, including the static random access memory (SRAM1) (level1), the SRAM2 (level2), and the XO32 and the RTC (level3), and the on-chip SCVR is shut down for power saving. The measurements show that compared with the conventional flat architecture, the dynamic voltage-stacking scheme reduces the sleep current by 38% under the same circumstances, and it also improves ULPMark-CP score by 23.6%, which is higher than the top1 in the ULPMark score list.

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6–3.6-μW/DMIPS 40–80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode

Preventing device obsolescence in Internet-of-things (IoT) is mandatory for its massive deployment to be ecologically sustainable. This calls for ultralow-power (ULP) reprogrammable microcontroller units (MCUs) for long lifetime, yet with sufficient computing performance to extract the meaningful information from the sensed data before transmitting it to the cloud. In this article, we present the SleepRunner MCU with logic/memory/power management co-optimization for best exploitation of the forward back biasing (FBB) capability in fully-depleted silicon-on-insulator (FDSOI) technologies. For low active power, we use ultralow-voltage (ULV) low- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> logic with upsized gate length and asymmetric FBB, a ULP SRAM macro with low read-access energy and switched-capacitor voltage regulators (SCVRs) for ULV supply generation from a single I/O voltage. The custom ULP SRAM macro is based on an ultralow-leakage (ULL) FBB-compatible bitcell for low SRAM retention power. In addition, a dual-loop digital unified frequency/back-bias regulation (UFBR) system efficiently compensates process and temperature variations with short wakeup from the zero-back-bias deep-sleep mode. Performance is measured for a synthetic benchmark and biomedical inference applications. The measured 40-MHz 2.6- μW/DMIPS (3.3 μW/MHz) active and 131-nW/kB deep-sleep power consumptions with CPU state retention are respectively 3 × and 2.5 × lower than for a conventional MCU design in this technology. This demonstrates the interest of 28-nm FDSOI with the proposed FBB-driven system optimization for ULP MCUs.

A Monolithic Resonant Switched-Capacitor Voltage Regulator With Dual-Phase Merged-LC Resonator

Fully integrated voltage regulation, while important for a number of applications, is challenging due to the limitations of on-chip passive components, particularly inductors. This work demonstrates a new direction in passive-component integration through the design and implementation of a silicon-integrated merged-LC resonator, used in a resonant switched-capacitor voltage regulator. The merged-LC resonator combines flying capacitance and inductance into a single structure to reduce ac resistive losses, achieving higher efficiency and power density. The voltage regulator is implemented in a 0.18-μm CMOS process and achieves 85.5% efficiency at 0.47 W without off-chip passive components. Light-load efficiency is extended through the use of OFF-time modulation (OTM); the design achieves <; 40-mV under-/over-shoot during 2-50-mA/4-μs load transients.

Analysis and Design Method of Multiple-Output Switched-Capacitor Voltage Regulators With a Reduced Number of Power Electronic Components

This paper presents a study of compact multiple-output switched-capacitor voltage regulators (MOSCVRs). Two methods to produce multiple outputs with an SCVR and their effects on performance – power efficiency and cross-regulation, are examined with output impedance analysis. Moreover, to help a circuit designer to implement a compact MOSCVR, a design method to determine the number of outputs and their conversion ratios is also proposed in this work. To verify this method, we demonstrate the design of an example compact MOSCVR. The MOSCVR is capable of simultaneously producing four different output voltages from a single input power supply with only two flying capacitors and twelve switches. The study presented in this work provides not only comprehensive insight but also guidance to find the suitable topology of a compact MOSCVR.

A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor Crossing Technique for Enhanced Power Efficiency

This paper presents a dual-output switched-capacitor voltage regulator (DOSCVR) with a new flying capacitor crossing technique (FCCT) to improve power efficiency. With the FCCT, the power loss of the DOSCVR is reduced by 28%, increasing the power efficiency by 7% compared with the power efficiency of the conventional method that generates two voltages using independent single-output SCVRs. This enhanced efficiency results in no area penalty since the total flying capacitance remains unchanged. A prototype is then implemented in a 0.13- $\mu \text{m}$ CMOS process to validate the proposed scheme. The prototype simultaneously produces two regulated voltages of 0.44 and 0.88 V from an input voltage of 1.5 V. The output voltages are regulated by low-bound regulation with frequency modulation. The maximum output current is 12 mA with a total flying capacitance of 0.98 nF, and the measured peak efficiency is 78%.

FOPAC: Flexible On-Chip Power and Clock

A novel flexible on-chip power and clock ( FOPAC ) generation and distribution circuit is proposed to enable fast dynamic voltage and frequency scaling (DVFS). FOPAC utilizes resonant rotary clocks (ReRoCs) along with multi-phase voltage regulators (MPVR) for the clock and power generation and distribution. The locally distributed ReRoCs provide the required clock phases to the MPVR, and the MPVR provides the required voltage levels to the ReRoC, providing spatial and temporal flexibility for fast DVFS. The ReRoC and MPVR share the on-chip fly capacitor of the switched capacitor voltage regulators to achieve greater frequency scaling at run-time while reducing the overhead. The FOPAC architecture is evaluated on industrial designs demonstrating a <2 ns DVFS switching time.

Issue: Selected paper of OIPE 2016 on modeling and optimal design of electromagnetic and electronic devices

Issue: Selected paper of OIPE 2016 on modeling and optimal design of electromagnetic and electronic devices

High-Efficiency Fully Integrated Switched-Capacitor Voltage Regulator for Battery-Connected Applications in Low-Breakdown Process Technologies

Conventional implementations of fully integrated, battery-connected, switched-capacitor voltage regulators (SCVRs) require either thick-oxide mosfet s or stacked thin-oxide mosfet s as power switches to sustain the voltage stress induced by a nominal 3.7-V Li-ion battery voltage. These approaches, however, exacerbate power loss, thus unable to achieve good power efficiency. Therefore, this paper proposes a solution to overcome the breakdown issue while improving the power efficiency by using only nonstacked, thin-oxide mosfet s. This is realized by using a three-state, low-voltage-stress SCVR with a cross-phase-switching technique to decrease the output impedance and increase the total equivalent capacitance in a multiphase configuration. A prototype 3:1 SCVR is implemented fully on-chip in a standard 130-nm CMOS process. The chip is capable of delivering a maximum load current of 45 mA with an input voltage range from 3.2 to 4 V. Measurement results show 78–80% efficiency over a range of output power 4–28 mW, and a power density up to 38 mW/nF. The measured output ripple is 30–50 mV over a load range of 11–45 mA, and the measured voltage droop is 69 mV with 200-ns settling time under a 13-mA load step.

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to $V_{{\mathrm{DD}}}$ , while its 4-kB ROM and the 16-kB SRAM are powered from $V_{{\mathrm{DD}}}$ to 2 $V_{{\mathrm{DD}}}$ . Since the memory and logic will, in general, draw different supply currents, the midrail $V_{{\mathrm{DD}}}$ is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and $V_{{\mathrm{DD}}}$ . Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 $\times $ . Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.

Fully Integrated on-Chip Switched DC–DC Converter for Battery-Powered Mixed-Signal SoCs

This paper presents a fully integrated on-chip switched-capacitor (SC) DC–DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (VL_dw) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (VL_dw). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC–DC converter is designed and simulated using high-voltage 0.35 μm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (IL = 15 mA at VL_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future data centers. On-chip switched capacitor converters can enable such granular power delivery with per-core regulation given a high efficiency, high power density, fast response time, and high output power converter design. This paper details the implementation of an on-chip switched capacitor voltage regulator in a $32\,\mathrm{n}\mathrm{m}$ SOI CMOS technology with deep trench capacitors. A novel feedforward control for reconfigurable switched capacitor converters is presented. The feedforward control reduces the output voltage droop following a transient load step. This leads to a reduced minimum microprocessor supply voltage, thereby reducing the overall power consumption of the microprocessor. The implemented on-chip switched capacitor voltage regulator provides a $0.7-1.1$ V output voltage from $1.8$ V input. It achieves a $85.1\%$ maximum efficiency at $3.2\,\mathrm{W}\mathrm{/}\mathrm{m}\mathrm{m}^2$ power density, a subnanosecond response time with improved minimum supply voltage capability, and a maximum output power of $10\,\mathrm{W}$ . For an output voltage of $850\,\mathrm{m}\mathrm{V}$ , the feedforward control reduces the required voltage overhead by $60\,\mathrm{m}\mathrm{V}$ for a transient load step from $10\%$ to $100\%$ of the nominal load. This can reduce the overall power consumption of the microprocessor by $7\%$ .

A compact implementation of a negative switched-capacitor voltage regulator dedicated to body-biasing of CMOS circuits

A fully integrated negative voltage regulator dedicated to body-biased circuits in FDSOI is proposed and validated through simulation. The regulator comprises an original negative switched-capacitor converter with a frequency modulation control loop. It can be digitally programmed by step of 100mV in 100μs time-scale from 100mV to 1.3V of negative voltage. The maximum overall power consumption is 20μA to drive 1mm2 of digital load.

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters

This paper introduces a technique, called scalable parasitic charge redistribution (SPCR), that reduces the parasitic bottom-plate losses in fully integrated switched-capacitor (SC) voltage regulators up to any desired level. This is realized by continuously redistributing the parasitic charge in-between phase-shifted converter cores. Because earlier models described the ratio of this parasitic coupling to the flying capacitance as the only limiting factor on the achievable fully integrated efficiency, the use of SPCR allows SC converters to achieve efficiencies previously deemed impossible. Transistor leakage is shown to be another limiting factor and is added to existing models which are then used to prove the effectiveness of SPCR over a wide range of power densities (up to 10 W/mm2) and technological parameters. The implementation of SPCR requires little overhead thanks to the use of charge redistribution buses. A 1/2 converter is fabricated in a 40 nm bulk CMOS technology that demonstrates SPCR by achieving a record efficiency for fully integrated closed-loop SC converters of 94.6%.

A Fully Integrated Switched-Capacitor Regulator With Frequency Modulation Control in 28-nm FDSOI

The fully integrated switched capacitor voltage regulator comprises power cells distributed as a ring around the digital area to supply while the MIM capacitors are stacked above. Multiratio cells provide a wide output voltage range from $0.2$ to $1.1\;{\rm V}$ with an input voltage of $1.8\;{\rm V}$ . A frequency modulation control loop is designed with proportional-integral control. Sampled-data modeling is used to derive the necessary transfer functions to build the control loop. A primarily test chip is fabricated in 28-nm FDSOI technology to evaluate the design. A power density of $310\;{\text{mW/}}{\text{mm}^2}$ is achieved at $72.5\%$ peak efficiency with a silicon area overhead of $11.5\%$ .

A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering

In this work, a switched-capacitor voltage regulator (SCVR) that dithers flying capacitance to reduce output voltage ripple is presented, and the benefits of such ripple reduction are investigated. In the proposed technique, SC converters are designed to run at the maximum available frequency, and the flying capacitance for different phases is adjusted according to load current change through comparators and a digital controller. The proposed technique is demonstrated in a 65 nm test chip consisting of a 40-phase SCVR with 4b capacitance modulation (CM) and a 2:1 conversion ratio. On-chip circuits for ripple measurement and load performance monitoring were included to accurately assess the magnitude and impact of ripple reduction. Measurement results show that at a 2.3 V input, an on-chip ripple magnitude of 6–16 mV at 1 V output is achieved for 11–142 mA load. Peak efficiency is 70.8% at a power density of $0.187\;{\text{W/m}}{{\text{m}}^{2}}$ .

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator

A digitally-controlled fully integrated voltage regulator (IVR) enables wide autonomous DVFS in a 22 nm graphics execution core. Part of the original power header is converted into a hybrid power stage to support digital low-dropout (DLDO), and switched-capacitor voltage regulator (SCVR) modes, in addition to the original bypass and sleep modes. Using voltage sensing, tunable replica circuit, or a core warning signal, the IVR detects and quickly responds to fast voltage droops to support fast dynamic workload changes without performance degradation. In a prototype, a 3D graphics execution core is powered up by the proposed hybrid IVR demonstrating measured 26% and 82% reduction in core energy in the turbo and the near-threshold voltage (NTV) modes, respectively. The total area overhead of the proposed hybrid IVR is 4% of the core compared to 2% from the original power header. Our digitally assisted control for the droop response shows ${\sim}$ 75% core frequency improvement at 0.84 V.

Resonant Switched-Capacitor Voltage Regulator With Ideal Transient Response

A new, small and efficient voltage regulator, realized using a resonant switched-capacitor converter technology, is introduced. Voltage regulation is implemented by means of simple digital pulse density modulation. It displays an ideal transient response with a zero-order nature to all disturbance types. The newly developed topology acts as a gyrator with a wide range of voltage conversion ratios (below as well as above unity) with constant efficiency characteristics for the entire operation range. The operation of the voltage regulator is verified on a 20 W experimental prototype, demonstrating ideal transient recovery without over/undershoots in response to load and line transients. Simple design guidelines for the voltage regulation system are provided and verified by experiments.

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS

Switch conductance modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, in 22 nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switch-size scaling scheme for maximum efficiency tracking across a wide range of voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures and, (ii) a simple active ripple mitigation technique that modulates the gate drive of select MOSFET switches effectively in all conversion modes. Efficiency improvements up to 15% are measured under low output voltage and load conditions. Load-independent output ripple of $ 50 mV is achieved, enabling reduced interleaving. Test chip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements.

Sampled-Data Modeling of Switched- Capacitor Voltage Regulator With Frequency-Modulation Control

The development of systems-on-chip requires embedded power management solutions due to the large number of power domains. The switched-capacitor voltage regulator is a suitable candidate as capacitors may be integrated whereas inductors still suffer limitations in that respect. Literature covers proposals of optimized power stages and several dedicated controllers for switched-capacitor DC-DC converters. Unfortunately the results do not cover systematic stability analyses. The paper proposes an original and systematic approach for the stability analysis of a switched-capacitor voltage regulator using sampled-data modeling. An application is given for a one-phase converter with a frequency-modulation based controller. The stability of the open-loop and closed-loop model is proposed and can be extended to multi-phase configurations.

System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near- &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$V_{t}$&lt;/tex-math&gt;&lt;/inline-formula&gt; Computing

This brief proposes to jointly optimize a switched capacitor voltage regulator module (SC-VRM) combined with a compute core to minimize system energy per instruction. Past work seeking to optimize system energy efficiency has focused on separately maximizing SC-VRM efficiency or operating the compute core at its minimum energy operating point (MEOP). We first propose and verify a core-aware SC-VRM energy model, which explicitly accounts for throughput constraints. Second, we perform joint optimization considering throughput unconstrained applications (TUA) and throughput constrained applications (TCAs). We show that, for TUA, the system MEOP (S-MEOP) voltage is different from both the core MEOP (C-MEOP) and VRM maximum efficiency point (V-MEP) voltages, and operating at S-MEOP achieves 12.3% and 21.8% energy savings compared with C-MEOP and V-MEP, respectively. For TCA, S-MEOP is achieved at the same voltage as C-MEOP but different from the voltage for V-MEP, and 38.9% energy savings can be obtained by operating at S-MEOP.