Switched-capacitor Networks Research Articles

A Digitally Testable $\Sigma-\Delta$ Modulator Using the Decorrelating Design-for-Digital-Testability

This paper demonstrates a digitally testable second-order Σ - Δ modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ - Δ modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Σ - Δ modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> T MUT only consists of 13 switches.

Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.

A Decorrelating Design-for-Digital-Testability Scheme for $\Sigma{-}\Delta$ Modulators

This paper presents a novel decorrelating design-for-digital-testability (D3T) scheme for Sigma-Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma-Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than -5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D3T scheme has the potential to test moderate nonlinearity. The proposed D3T scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.

High-speed low-power CMOS comparator dedicated to 10 bit 20 MHz pipeline ADCs for RF WLAN applications

This article describes and analyses a low power and high speed comparator. The designed comparator is intended to be implemented in a 10 bit 20 MHz Pipeline Analogue-to-Digital Converter dedicated to RF Wireless Local Area Network (WLAN) applications. This comparator is based on the switched capacitor network using a two-phase non-overlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8 µm CMOS AMS process parameters, with a power supply voltage of 5 V and an input common mode of 2–3 V, show that this comparator exhibits a propagation delay of 17.3 ns, an offset voltage of about 77.3 mV, a good accuracy and a low power consumption of about 0.8 mW. The predicted performance is verified by analyses and simulations using PSPICE tool.

A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design

This works presents an integrated 0.18 μ m CMOS 2-PPM demodulator based on a switched capacitor network for an energy detection impulse-radio UWB receiver. The circuit has been designed using a top-down methodology that allows to discover the impact of low-level non-idealities on system-level performance. Through the use of a mixed-signal simulation environment, performance figures have been obtained which helped evaluate the influence at system level of the non-idealities of the most critical block. Results show that the circuit allows the replacement of the ADC typically employed in energy detection receivers and provides about infinite equivalent quantization resolution. The demodulator achieves 190 pJ/bit at 1.8 V.

Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture

Notice of Violation of IEEE Publication Principles<br><br>"A Low Reference Spurs 15 GHz 0.13 μm CMOS Frequency Synthesizer Using a Fully-Sampled Feed-Forward Loop Filter Architecture"<br>by Maxim, A.<br>in the IEEE Journal of Solid-State Circuits,<br>Volume 42, Issue 11, Nov. 2007 Page(s):2503 - 2514<br><br>After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.<br><br>Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:<br><br>C. Turinici, D. Smith, S. Dupue<br><br>Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.<br><br>Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.<br><br>Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references. <br/> A wide tuning range, low phase noise and spurs, multi-gigahertz frequency synthesizer was realized in 0.13 μm CMOS using a fully-sampled feed-forward loop filter. Both the integral and proportional loop filter paths use sample and hold switched-capacitor networks that completely isolate the oscillator from the charge-pump switching transients. The sampled nature of the filter, together with a digital domain implementation of the ripple-filtering pole spread the impulsive energy coming from the charge-pump current injection over several reference clock cycles, resulting in a dramatic reduction of the oscillator control signal ripple and thus a very low reference spur level. A multi-regulator PLL architecture reduces the supply injected noise and spurious tones, allowing the integration of the synthesizer on the same die with a large digital core, as required by modern single-chip receiver SoCs. PLL specifications include: < 1deg rms double-sided integrated phase noise from 1 kHz to 10 MHz, -85 dBc reference spurs, < -80 dBc supply injected spurs, 300 times 750 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area and < 100 mW power dissipation from a single 2.5 V supply.

Efficient parametric fault detection in switched-capacitor filters

Advances in technology and IC design techniques have allowed for sophisticated analog and digital functions in a single chip, in which switched-capacitor (SC) networks perform fundamental operations such as filtering and A/D and D/A conversion. As a result, considerable effort has gone into improving test coverage and testable circuit design in general and SC networks in particular. This article presents an alternative SC-filter-testing methodology, which not only accurately detects but also locates parametric faults, using little additional circuitry. Based on structurally all-pass building blocks, the proposed technique fits into the DFT category. It uses considerably less additional circuitry for testing than other approaches because the testing procedure consists of forming notch filters out of existing second-order all-pass sections. Moreover, it does not require reconfiguration of the circuit under test, making it suitable for online testing. The testing scheme also belongs to the multifrequency analysis class, but it requires neither optimization nor sensitivity computations because the filter transfer function's synthesis procedure naturally reveals the optimum test frequencies and nodes. The scheme is readily extendable to other discrete- or continuous-time structures based on all-pass filters.

Continuous-time common-mode feedback for high-speed switched-capacitor networks

This paper deals with the design of a continuous-time common-mode feedback (CMFB) for switched-capacitor networks. Its reduced input capacitance decreases the capacitive load at the output of the fully differential amplifier, improving its achievable gain-bandwidth (GBW) product and slew rate. This topology is more suitable for high-speed switched-capacitor applications when compared to a conventional switched-capacitor CMFB, enabling operation at higher clock frequencies. Additionally, it provides a superior rejection to the negative power supply noise (PSRR/sup -/). The performance of the CMFB is demonstrated in the implementation of a second-order 10.7-MHz bandpass switched-capacitor filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72 MHz while providing a dynamic range of 59 dB and a PSRR/sup -/>22 dB. Both circuits were fabricated in 0.35-/spl mu/m CMOS technology.

Numerical algorithm for noise analysis of switched-capacitor networks

An algorithm for computerized noise analysis of switched-capacitor networks is presented. The analysis is entirely performed in the frequency domain and the passage from the continuous-time domain to the discrete-time domain is accomplished through numerical integration. The algorithm offers the capability of analyzing circuits incorporating correlated double-sampling or more generally multiple sampling. Numerical calculations consist of standard linear noise analysis and post-processing of the data to account for sample-and-hold and tracking effects. The assumptions fundamental to the analysis are fast and complete charge transfer and also stationarity or cyclostationarity of continuous-time noise sources. Numerical results for stray-insensitive and correlated double-sampling integrators are provided to illustrate the algorithm performance.

Forward- and backpropagation in a silicon dendrite

We have developed an analog very-large-scale integrated (aVLSI) electronic circuit that emulates a compartmental model of a neuronal dendrite. The horizontal conductances of the compartmental model are implemented as a switched capacitor network. The transmembrane conductances are implemented as transconductance amplifiers. The electrotonic properties of our silicon cable are qualitatively similar to those of the ideal passive cable that is commonly used to model mathematically the electrotonic behavior of neurons. In particular the propagation of excitatory postsynaptic potentials is realistic, and we are easily able to emulate such classical synaptic integration models as direction selectivity. We are also able to emulate the backpropagation into the dendrite of single somatic spikes and bursts of spikes. Thus, this silicon dendrite is suitable for incorporation in detailed silicon neurons operating in real-time; in particular for the emulation of forward- and backpropagating electrical activities found in real neurons.

Adjoint network of periodically switched linear circuits with applications to noise analysis

In this paper, Tellegen's theorem for multiphase periodically switched linear (PSL) circuits in phasor domain and the adjoint network of PSL circuits are developed. Two new theorems are introduced and theoretical proofs are given. The first theorem, called the transfer function theorem, gives an efficient way to calculate the transfer functions from multiple inputs to a single output of PSL circuits. This theorem is the generalization of a similar result known for linear time-invariant and ideal switched capacitor networks. A major contribution of this paper is the second theorem, called the frequency reversal theorem, which gives an efficient way to compute the aliasing transfer functions of linear periodically time-varying circuits. The use of both of these theorems results in an efficient algorithm for noise analysis of linear periodically time-varying circuits in the frequency domain. The algorithm handles general PSL circuits, including switched capacitor and switched current networks with both white and 1/f noise sources. It has been implemented in a computer program. The output noise power of practical PSL circuits is analyzed and the results are compared with published measurement data.

The Total Capitance, Transient and Frequency Response of MFB, FDNR and Leaperog Techniques For Bilinear Switched-Capacitor Network

The Total Capitance, Transient and Frequency Response of MFB, FDNR and Leaperog Techniques For Bilinear Switched-Capacitor Network

Noise analysis of ideal switched-capacitor networks

This paper presents a method for computing the noise power spectral density (PSD) in switched-capacitor networks, Explicit formulas are developed for both white and 1/f noise sources. The 1/f noise is handled directly in the formulation without having to approximate its PSD by using a noise shaping filter. The technique eliminates the need for computing eigenvalues or matrix exponentials as well as solving bilateral matrix equations, and thereby leads to a numerically efficient algorithm. The noise sources considered here are the ON-resistances of MOS switches and the input referred noise PSD's of operational amplifiers (opamps). Experiments are carried out to demonstrate the validity of the formulation for both white and 1/f input noise.

Automatic symbolic analysis of SC networks using a modified nodal approach

This paper presents a symbolic analysis of Switched-Capacitor (SC) circuits in the z-domain using Modified Nodal Approach (MNA). We have selected the MNA method as one of the widely established approaches in circuit analysis. The analyses are performed using SymsimC symbolic simulator which also enables s-domain network analysis. Macromodels of various SC-basic building blocks are utilized to decrease the number of equations describing the circuit which in turn relaxes the analysis. The results of simulations are demonstrated on a benchmark example of an SC-network that was frequently used in previous papers. The new feature imposed with this work is the examination of the influence of finite gain and bandwidth of operational amplifiers on the circuit's behaviour. The obtained results could serve as a valuable aid to the designer in the assessment of designed circuit performance.

A low-power CMOS nine-channel 40-MHz binary detection system with self-calibrated 500-μV offset

For application in high-energy physics experiments, this paper describes the design of a nine-channel binary detection system featuring a fully differential 300-/spl mu/W, 40-MHz comparator whose offset voltage is reduced to less than 500 /spl mu/V by means of a digitally controlled calibration system. Besides the comparator, each channel also includes an input waveshaping high-pass filter for improved detection performance in the particle-radiated operating environment. To save area and power, this is realized by a passive switched-capacitor polyphase network with time-interleaved operation. Two prototype chips have been realized in a 1.2-/spl mu/m CMOS technology. One chip includes nine filter-comparator channels that occupy 0.4 mm/sup 2/ and at 40 MHz dissipate about 2.7 mW. The other chip contains the calibration system that generates all control signals for offset correction of the filter/comparator channels and occupies 1.4 mm/sup 2/.

Development of efficient switched network and mixed-mode simulators

The philosophy, theory and numerical techniques required in the development of a contemporary suite of simulators for switched network and mixed-mode analysis are described in detail. The evolution of a general simulator, SCNAP4, from earlier software is outlined, and comprehensive sensitivity analysis of switched capacitor (SC) and switched current (SI) networks is shown, together with full noise analysis for large SC and SI networks. An extension into semi-symbolic analysis of non-ideal SC and SI circuits is shown to be feasible, with good accuracy being maintained for large networks. The highly efficient techniques are then utilised for large signal distortion analysis and implemented in the SCNAPDIS simulator. The natural progression of the software development subsequently leads to SCNAP5, which interfaces with the commercial logic simulator Verilog to produce a most effective mixed-mode simulator capable of delivering very detailed analysis of mixed-mode SC and SI circuits. In the development of this latest suite of SCNAP software much effort has been directed towards producing highly efficient algorithms, very versatile packages and a uniform structure with a simple user interface. All the software is written in C. A variety of examples are given to illustrate the wide range of application of the software.

A switched capacitor harmonic compensation part for switching supplies

A new approach based on switched capacitor network to harmonic compensation for switching supplies is presented in the paper. The basic principle is discussed. SPICE simulation is applied to analyze the behaviour of the switched capacitor harmonic compensation part.

Symbolic analysis of switched-capacitor networks using compacted nodal analysis in the s-domain

This short paper presents a method that makes it possible to analyze switched-capacitor (SC) networks in discrete time using compacted nodal analysis in continuous time. Our objective is to perform time-discrete analysis in the z-domain using any symbolic analysis tool (e.g. CASCA) intended for analysis of time-continuous networks in the s-domain. A new equivalent analog circuit is used to describe the switched capacitors in the s-domain with z=s instead of z=e/sup sT/ which gives a simple translation between the two domains. Two SC examples are considered: an inverting amplifier and a biquad.

Multiresolution image sensor

The development of the CMOS active pixel sensor (APS) has, for the first time, permitted large scale integration of supporting circuitry and smart camera-functions on the same chip as a high-performance image sensor. This paper reports on the demonstration of a new 128/spl times/128 CMOS APS with programmable multiresolution readout capability. By placing signal processing circuitry on the imaging focal plane, the image sensor can output data at varying resolutions which can decrease the computational load of downstream image processing. For instance, software intensive image pyramid reconstruction can be eliminated. The circuit uses a passive switched capacitor network to average arbitrarily large neighborhoods of pixels which can then be read out at any user-defined resolution by configuring a set of digital shift registers. The full resolution frame rate is 30 Hz with higher rates for all other image resolutions. The sensor achieved 80 dB of dynamic range while dissipating only 5 mW of power. Circuit error was less than -34 dB and introduced no objectionable fixed pattern noise or other artifacts into the image.

An AHDL-based methodology for computer simulation of switched-capacitor filters

In this paper an AHDL-based method for computer simulation of switched-capacitor networks is described. It is based on the transformation of these circuits from the sampled-data domain to the continuous-time domain and on the description of the obtained network with a behavioural language. This approach uses a general-purpose circuit simulator to analyse accurately and efficiently a wide range of circuits in both the frequency and the time domain. Reduced computation time is also ensured. The performance and the advantages of this method are illustrated by presenting and discussing a number of simulation examples.